PIC16C84-04I/SO Microchip Technology, PIC16C84-04I/SO Datasheet - Page 44

• Manufacturer Part Number: PIC16C84-04I/SO
• Description: IC MIC CTL EEPM 1K 4MHZ IT18SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16C84-04I/SO

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 4MHz
• Peripherals: POR, WDT
• Number Of I /o: 13
• Program Memory Size: 1.75KB (1K x 14)
• Program Memory Type: EEPROM
• Eeprom Size: 64 x 8
• Ram Size: 36 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 18-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Data Converters: -
• Connectivity: -

PIC16C84
8.9
The PIC16C84 has 4 sources of interrupt:
• External interrupt RB0/INT pin
• TMR0 overflow interrupt
• PORTB change interrupts (pins RB7:RB4)
• EEPROM write complete interrupt
The interrupt control register (INTCON) records
individual interrupt requests in flag bits. It also contains
the individual and global interrupt enable bits.
The global interrupt enable bit, GIE (INTCON<7>)
enables (if set) all un-masked interrupts or disables (if
cleared) all interrupts. Individual interrupts can be
disabled through their corresponding enable bits in
INTCON register. Bit GIE is cleared on reset.
The “return from interrupt” instruction, RETFIE, exits
interrupt routine as well as sets the GIE bit, which re-
enable interrupts.
The RB0/INT pin interrupt, the RB port change inter-
rupt and the TMR0 overflow interrupt flags are con-
tained in the INTCON register.
DS30445C-page 44
Interrupts
When an interrupt is responded to; the GIE bit is
cleared to disable any further interrupt, the return
address is pushed onto the stack and the PC is loaded
with 0004h. For external interrupt events, such as the
RB0/INT pin or PORTB change interrupt, the interrupt
latency will be three to four instruction cycles. The exact
latency depends when the interrupt event occurs
(Figure 8-16). The latency is the same for both one and
two cycle instructions. Once in the interrupt service
routine the source(s) of the interrupt can be determined
by polling the interrupt flag bits. The interrupt flag bit(s)
must be cleared in software before re-enabling
interrupts to avoid infinite interrupt requests.
LOOP
Note 1: Individual interrupt flag bits are set
Note 2: If an interrupt occurs while the Global
BCF
BTFSC INTCON,GIE
GOTO
regardless
corresponding mask bit or the GIE bit.
Interrupt Enable (GIE) bit is being cleared,
the GIE bit may unintentionally be
re-enabled by the user’s Interrupt Service
Routine (the RETFIE instruction). The
events that would cause this to occur are:
1.
2.
3.
The method to ensure that interrupts are
globally disabled is:
1.
INTCON,GIE
LOOP
An instruction clears the GIE bit while
an interrupt is acknowledged
The
Interrupt vector and executes the
Interrupt Service Routine.
The
completes with the execution of the
RETFIE instruction. This causes the
GIE bit to be set (enables interrupts),
and the program returns to the
instruction after the one which was
meant to disable interrupts.
Ensure that the GIE bit is cleared by
the instruction, as shown in the
following code:
program
Interrupt
of
1997 Microchip Technology Inc.
;Disable All
;
;All Interrupts
;
;NO, try again
;
;
;
the
Interrupts
Disabled?
Yes, continue
with program
flow
branches
Service
status
of
Routine
to
their
the