MC9S08GT8ACFBE Freescale Semiconductor, MC9S08GT8ACFBE Datasheet - Page 98

• Manufacturer Part Number: MC9S08GT8ACFBE
• Description: IC MCU 8K FLASH 1K RAM 44-QFP
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08GT8ACFBE

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-QFP
• Processor Series: S08GT
• Core: HCS08
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: I2C/SCI/SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 36
• Operating Supply Voltage: 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWS08
• Development Tools By Supplier: M68EVB908GB60E, M68DEMO908GB60E
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• For Use With: M68DEMO908GB60E - BOARD DEMO MC9S08GB60M68EVB908GB60E - BOARD EVAL FOR MC9S08GB60
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

1
Parallel Input/Output
98
PTGDD[3:0]
PTGSE[3:0]
Although PTGDD0 is implemented, this bit actually has no effect on the operation of PTG0/BKGD.
Reset
Reset
Field
Field
3:0
3:0
W
W
R
R
Slew Rate Control Enable for Port G Bits — For port G pins that are outputs, these read/write control bits
determine whether the slew rate controlled outputs are enabled. For port G pins that are configured as inputs,
these bits are ignored.
0 Slew rate control disabled.
1 Slew rate control enabled.
Data Direction for Port G Bits — These read/write bits control the direction of port G pins and what is read for
PTGD reads.
0 Input (output driver disabled) and reads return the pin value.
1 Output driver enabled for port G bit n and PTGD reads return the contents of PTGDn.
0
0
7
0
7
0
Figure 6-30. Slew Rate Control Enable for Port G (PTGSE)
0
0
0
0
6
6
Figure 6-31. Data Direction for Port G (PTGDD)
Table 6-24. PTGDD Field Descriptions
Table 6-23. PTGSE Field Descriptions
MC9S08GT16A/GT8A Data Sheet, Rev. 1
0
0
0
0
5
5
0
0
0
0
4
4
Description
Description
PTGDD3
PTGSE3
3
0
3
0
PTGDD2
PTGSE2
0
0
2
2
PTGDD1
PTGSE1
Freescale Semiconductor
0
0
1
1
PTGSE0
PTGDD0
Note
0
0
0
0
(1)