DSPIC30F5015-30I/PT Microchip Technology, DSPIC30F5015-30I/PT Datasheet - Page 100

• Manufacturer Part Number: DSPIC30F5015-30I/PT
• Description: IC DSPIC MCU/DSP 66K 64TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F5015-30I/PT

• Program Memory Type: FLASH
• Program Memory Size: 66KB (22K x 24)
• Package / Case: 64-TFQFP
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 30 MIPs
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 52
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Product: DSCs
• Data Bus Width: 16 bit
• Processor Series: DSPIC30F
• Core: dsPIC
• Maximum Clock Frequency: 30 MHz
• Number Of Programmable I/os: 52
• Data Ram Size: 2 KB
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, DM240002, DM330011
• Minimum Operating Temperature: - 40 C
• Package: 64TQFP
• Device Core: dsPIC
• Family Name: dsPIC30
• Maximum Speed: 30 MHz
• Operating Supply Voltage: 3.3|5 V
• Interface Type: CAN/I2C/SPI/UART
• On-chip Adc: 16-chx10-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT64PT5 - SOCKET TRAN ICE 64MQFP/TQFPAC164319 - MODULE SKT MPLAB PM3 64TQFPAC30F008 - MODULE SKT FOR DSPIC30F 64TQFPDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: DSPIC30F501530IPT

Complementary mode by default upon a device Reset.
dsPIC30F5015/5016
15.6
In the Complementary mode of operation, each pair of
PWM outputs is obtained by a complementary PWM
signal. A dead time may be optionally inserted during
device switching, when both outputs are inactive for a
short period (Refer to Section 15.7 “Dead-Time
Generators”).
In Complementary mode, the duty cycle comparison
units are assigned to the PWM outputs as follows:
• PDC1 register controls PWM1H/PWM1L outputs
• PDC2 register controls PWM2H/PWM2L outputs
• PDC3 register controls PWM3H/PWM3L outputs
• PDC4 register controls PWM4H/PWM4L outputs
The Complementary mode is selected for each PWM
I/O pin pair by clearing the appropriate PMODx bit in the
PWMCON1 SFR. The PWM I/O pins are set to
15.7
Dead-time generation may be provided when any of the
PWM I/O pin pairs are operating in the Complementary
Output mode. The PWM outputs use Push-Pull drive
circuits. Due to the inability of the power output devices
to switch instantaneously, some amount of time must be
provided between the turn off event of one PWM output
in a complementary pair and the turn on event of the
other transistor.
The PWM module allows two different dead times to be
programmed. These two dead times may be used in
one of two methods described below to increase user
flexibility:
• The PWM output signals can be optimized for
• The two dead times can be assigned to individual
15.7.1
Each complementary output pair for the PWM module
has a 6-bit down counter that is used to produce the
dead-time insertion. As shown in Figure 15-4, each
dead-time unit has a rising and falling edge detector
connected to the duty cycle comparison output.
DS70149D-page 100
different turn off times in the high side and low
side transistors in a complementary pair of
transistors. The first dead time is inserted
between the turn off event of the lower transistor
of the complementary pair and the turn on event
of the upper transistor. The second dead time is
inserted between the turn off event of the upper
transistor and the turn on event of the lower
transistor.
PWM I/O pin pairs. This operating mode allows
the PWM module to drive different transistor/load
combinations with each complementary PWM I/O
pin pair.
Complementary PWM Operation
Dead-Time Generators
DEAD-TIME GENERATORS
15.7.2
The DTCON2 SFR contains control bits that allow the
dead times to be assigned to each of the
complementary outputs. Table 15-1 summarizes the
function of each dead-time selection control bit.
TABLE 15-1:
15.7.3
The amount of dead time provided by each dead-time
unit is selected by specifying the input clock prescaler
value and a 6-bit unsigned value. The amount of dead
time provided by each unit may be set independently.
Four input clock prescaler selections have been
provided to allow a suitable range of dead times, based
on the device operating frequency. The clock prescaler
option may be selected independently for each of the
two dead-time values. The dead-time clock prescaler
values are selected using the DTAPS<1:0> and
DTBPS<1:0> control bits in the DTCON1 SFR. One of
four clock prescaler options (T
may be selected for each of the dead-time values.
After the prescaler values are selected, the dead time
for each unit is adjusted by loading two 6-bit unsigned
values into the DTCON1 SFR.
The dead-time unit prescalers are cleared on the
following events:
• On a load of the down timer due to a duty cycle
• On a write to the DTCON1 or DTCON2 registers.
• On any device Reset.
DTS1A
DTS1I
DTS2A
DTS2I
DTS3A
DTS3I
DTS4A
DTS4I
comparison edge event.
Note:
Bit
Selects PWM1L/PWM1H active edge dead time.
Selects PWM1L/PWM1H inactive edge
dead time.
Selects PWM2L/PWM2H active edge dead time.
Selects PWM2L/PWM2H inactive edge
dead time.
Selects PWM3L/PWM3H active edge dead time.
Selects PWM3L/PWM3H inactive edge
dead time.
Selects PWM4L/PWM4H active edge dead time.
Selects PWM4L/PWM4H inactive edge
dead time.
DEAD-TIME ASSIGNMENT
DEAD-TIME RANGES
The user should not modify the DTCON1
or DTCON2 values while the PWM
module
Unexpected results may occur.
DEAD-TIME SELECTION BITS
is
© 2008 Microchip Technology Inc.
operating
Function
CY
, 2 T
CY
(PTEN
, 4 T
CY
or 8 T
=
1).
CY
)