PIC18F4455-I/P Microchip Technology, PIC18F4455-I/P Datasheet - Page 72

• Manufacturer Part Number: PIC18F4455-I/P
• Description: IC PIC MCU FLASH 12KX16 40DIP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F4455-I/P

• Program Memory Type: FLASH
• Program Memory Size: 24KB (12K x 16)
• Package / Case: 40-DIP (0.600", 15.24mm)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 35
• Eeprom Size: 256 x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SPI/I2C/EAUSART
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 35
• Number Of Timers: 4
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM163025
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 13-ch x 10-bit
• Package: 40PDIP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 48 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: I3-DB18F4550 - BOARD DAUGHTER ICEPIC3DM163025 - PIC DEM FULL SPEED USB DEMO BRDDVA18XP400 - DEVICE ADAPTER 18F4220 PDIP 40LD444-1001 - DEMO BOARD FOR PICMICRO MCUACICE0206 - ADAPTER MPLABICE 40P 600 MIL
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F2455/2550/4455/4550
TABLE 5-2:
DS39632E-page 70
OSCCON
HLVDCON
WDTCON
RCON
TMR1H
TMR1L
T1CON
TMR2
PR2
T2CON
SSPBUF
SSPADD
SSPSTAT
SSPCON1
SSPCON2
ADRESH
ADRESL
ADCON0
ADCON1
ADCON2
CCPR1H
CCPR1L
CCP1CON
CCPR2H
CCPR2L
CCP2CON
BAUDCON
ECCP1DEL
ECCP1AS
CVRCON
CMCON
TMR3H
TMR3L
T3CON
SPBRGH
SPBRG
RCREG
TXREG
TXSTA
RCSTA
Legend:
Note
File Name
1:
2:
3:
4:
5:
6:
7:
x = unknown, u = unchanged, - = unimplemented, q = value depends on condition. Shaded cells are unimplemented, read as ‘0’.
Bit 21 of the TBLPTRU allows access to the device Configuration bits.
The SBOREN bit is only available when BOREN<1:0> = 01; otherwise, the bit reads as ‘0’.
These registers and/or bits are not implemented on 28-pin devices and are read as ‘0’. Reset values are shown for 40/44-pin devices;
individual unimplemented bits should be interpreted as ‘-’.
RA6 is configured as a port pin based on various primary oscillator modes. When the port pin is disabled, all of the associated bits read ‘0’.
RE3 is only available as a port pin when the MCLRE Configuration bit is clear; otherwise, the bit reads as ‘0’.
RC5 and RC4 are only available as port pins when the USB module is disabled (UCON<3> = 0).
I
2
A/D Result Register High Byte
A/D Result Register Low Byte
Timer1 Register High Byte
Timer1 Register Low Byte
Timer2 Register
Timer2 Period Register
MSSP Receive Buffer/Transmit Register
MSSP Address Register in I
Capture/Compare/PWM Register 1 High Byte
Capture/Compare/PWM Register 1 Low Byte
Capture/Compare/PWM Register 2 High Byte
Capture/Compare/PWM Register 2 Low Byte
Timer3 Register High Byte
Timer3 Register Low Byte
EUSART Baud Rate Generator Register High Byte
EUSART Baud Rate Generator Register Low Byte
EUSART Receive Register
EUSART Transmit Register
C™ Slave mode only.
VDIRMAG
ECCPASE
ABDOVF
P1M1
PRSEN
CVREN
C2OUT
IDLEN
WCOL
GCEN
ADFM
CSRC
SPEN
RD16
RD16
IPEN
Bit 7
SMP
—
—
—
—
—
REGISTER FILE SUMMARY (CONTINUED)
(3)
SBOREN
T2OUTPS3
ACKSTAT
ECCPAS2
T3CCP2
P1M0
PDC6
SSPOV
CVROE
T1RUN
C1OUT
RCIDL
IRCF2
Bit 6
CKE
TX9
RX9
—
—
—
—
—
—
(3)
(3)
(2)
2
T2OUTPS2
ADMSK5
C™ Slave mode. MSSP Baud Rate Reload Register in I
T1CKPS1
ECCPAS1
T3CKPS1
ACKDT/
PDC5
SSPEN
VCFG1
ACQT2
RXDTP
DC1B1
DC2B1
IRCF1
IRVST
C2INV
CVRR
SREN
CHS3
TXEN
Bit 5
D/A
—
—
(3)
(7)
T2OUTPS1
ADMSK4
T1CKPS0
ECCPAS0
T3CKPS0
HLVDEN
ACKEN/
PDC4
CVRSS
VCFG0
ACQT1
DC1B0
DC2B0
TXCKP
IRCF0
C1INV
SYNC
CREN
CHS2
Bit 4
CKP
—
RI
P
(3)
(7)
T2OUTPS0
ADMSK3
T1OSCEN
CCP1M3
CCP2M3
PSSAC1
T3CCP1
HLVDL3
PDC3
SENDB
ADDEN
SSPM3
PCFG3
ACQT0
BRG16
RCEN/
OSTS
CHS1
CVR3
Bit 3
CIS
TO
—
S
(3)
(7)
ADMSK2
TMR2ON
T1SYNC
CCP1M2
CCP2M2
PSSAC0
T3SYNC
HLVDL2
PDC2
SSPM2
PCFG2
ADCS2
BRGH
FERR
CHS0
CVR2
IOFS
PEN/
Bit 2
CM2
R/W
PD
—
—
(3)
(7)
2
ADMSK1
PSSBD1
GO/DONE
T2CKPS1
C™ Master mode.
TMR1CS
TMR3CS
CCP1M1
CCP2M1
HLVDL1
PDC1
SSPM1
PCFG1
ADCS1
RSEN/
OERR
TRMT
SCS1
CVR1
WUE
Bit 1
POR
CM1
UA
—
(3)
(3)
(7)
© 2009 Microchip Technology Inc.
PSSBD0
T2CKPS0
SWDTEN
TMR1ON
TMR3ON
CCP1M0
CCP2M0
HLVDL0
PDC0
SSPM0
ABDEN
PCFG0
ADCS0
ADON
SCS0
CVR0
TX9D
RX9D
Bit 0
BOR
SEN
CM0
BF
(3)
(3)
0100 q000
0-00 0101
0q-1 11q0
xxxx xxxx
xxxx xxxx
0000 0000
0000 0000
1111 1111
-000 0000
xxxx xxxx
0000 0000
0000 0000
0000 0000
0000 0000
xxxx xxxx
xxxx xxxx
--00 0000
--00 0qqq
0-00 0000
xxxx xxxx
xxxx xxxx
0000 0000
xxxx xxxx
xxxx xxxx
--00 0000
0100 0-00
0000 0000
0000 0000
0000 0000
0000 0111
xxxx xxxx
xxxx xxxx
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0010
0000 000x
POR, BOR
--- ---0
Value on
on page
54, 198,
54, 198,
54, 199,
55, 143,
54, 285
54, 304
54, 136
54, 136
54, 131
54, 138
54, 138
54, 137
54, 207
54, 210
54, 274
54, 274
54, 265
54, 266
54, 267
55, 144
55, 144
55, 144
55, 144
55, 143
55, 246
55, 160
55, 161
55, 281
55, 275
55, 141
55, 141
55, 139
55, 247
55, 247
55, 256
55, 253
55, 244
55, 245
Details
54, 33
54, 46
207
208
209
151