PIC18F8390T-I/PT Microchip Technology, PIC18F8390T-I/PT Datasheet - Page 123

• Manufacturer Part Number: PIC18F8390T-I/PT
• Description: IC PIC MCU FLASH 4KX16 80TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F8390T-I/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, LCD, POR, PWM, WDT
• Number Of I /o: 66
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TFQFP
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: SPI, I2C, EUSART, AUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 66
• Number Of Timers: 1 x 8
• Operating Supply Voltage: 4.2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM163028
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit
• For Use With: XLT80PT3 - SOCKET TRAN ICE 80MQFP/TQFPDM163028 - BOARD DEMO PICDEM LCDAC164320 - MODULE SKT MPLAB PM3 80TQFPAC174011 - MODULE SKT PROMATEII 80TQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

TABLE 9-10:
TABLE 9-11:
© 2007 Microchip Technology Inc.
RE4/COM1
RE5/COM2
RE6/COM3
RE7/CCP2/
SEG31
Legend:
Note 1:
PORTE
LATE
TRISE
LCDCON
LCDSE3
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTE.
Pad Name
Name
O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input, TTL = TTL Buffer Input,
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Alternate assignment for CCP2 when the CCP2MX Configuration bit = 0.
LATE Data Output Register
PORTE Data Direction Register
Function
LCDEN
CCP2
SEG31
COM1
COM2
COM3
SE31
Bit 7
RE7
RE4
RE5
RE6
RE7
SUMMARY OF REGISTERS ASSOCIATED WITH PORTE
PORTE FUNCTIONS
(1)
Setting
TRIS
SLPEN
SE30
0
1
x
0
1
x
0
1
x
0
1
0
1
x
Bit 6
RE6
I/O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
WERR
SE29
Bit 5
RE5
Buffer
ANA
ANA
ANA
ANA
DIG
DIG
DIG
DIG
DIG
ST
ST
ST
ST
ST
PIC18F6390/6490/8390/8490
LATE<4> data output; disabled when LCD common enabled.
PORTE<4> data input.
Common 1 analog output for LCD.
LATE<5> data output; disabled when LCD common enabled.
PORTE<5> data input.
Common 2 analog output for LCD.
LATE<6> data output; disabled when LCD segment enabled.
PORTE<6> data input.
Common 3 analog output for LCD.
LATE<7> data output; disabled when LCD segment enabled.
PORTE<7> data input.
CCP2 compare output and CCP2 PWM output; takes priority over port data.
CCP2 capture input.
Segment 31 analog output for LCD.
SE28
Bit 4
RE4
—
SE27
Bit 3
CS1
—
—
—
SE26
Bit 2
CS0
—
—
—
Description
LMUX1
SE25
Bit 1
—
—
—
LMUX0
SE24
Bit 0
DS39629C-page 121
—
—
—
on Page
Values
Reset
62
62
62
64
64