PIC18F65J10-I/PT Microchip Technology, PIC18F65J10-I/PT Datasheet - Page 33

• Manufacturer Part Number: PIC18F65J10-I/PT
• Description: IC PIC MCU FLASH 16KX16 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F65J10-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 32KB (16K x 16)
• Package / Case: 64-TFQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 50
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SPI/I2C/EUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 50
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183022, DM183032
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 11-ch x 10-bit
• Package: 64TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 2.5|3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: MA180015 - MODULE PLUG-IN 18F87J10 FOR HPCAC162062 - HEADER INTRFC MPLAB ICD2 64/80PAC164327 - MODULE SKT FOR 64TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

6.0
 2009 Microchip Technology Inc.
Standard Operating Conditions
Operating Temperature: 25C is recommended
Param
P12
P13
P14
P16
P19
P20
Note 1:
No.
2:
T
T
T
T
T
T
Symbol
AC/DC CHARACTERISTICS AND TIMING REQUIREMENTS
FOR PROGRAM/VERIFY TEST MODE (CONTINUED)
HLD
SET
VALID
DLY
KEY
KEY
V
Section 2.1.1 “On-Chip Voltage Regulator” for more information.
V
regulator is used. AV
2
8
2
1
2
DDCORE
DD
must also be supplied to the AV
Input Data Hold Time from MCLR 
V
Data Out Valid from PGC 
Delay between Last PGC  and MCLR 
Delay from First MCLR to First PGC for
Key Sequence on PGD
Delay from Last PGC for Key Sequence on
PGD to Second MCLR 
DD
must be supplied to the V
Setup Time to MCLR 
DD
Characteristic
and AV
SS
should always be within ±0.3V of V
DDCORE
DD
pins during programming and to the ENVREG pin if the on-chip voltage
/V
CAP
pin if the on-chip voltage regulator is disabled. See
PIC18F6XJXX/8XJXX
Min
400
100
10
20
40
1
Max
—
—
—
—
—
—
DD
and V
Units
ms
s
ns
ns
ns
ns
SS
, respectively.
Conditions
DS39644L-page 33