PIC18F65J10-I/PT Microchip Technology, PIC18F65J10-I/PT Datasheet - Page 28

• Manufacturer Part Number: PIC18F65J10-I/PT
• Description: IC PIC MCU FLASH 16KX16 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F65J10-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 32KB (16K x 16)
• Package / Case: 64-TFQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 50
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SPI/I2C/EUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 50
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183022, DM183032
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 11-ch x 10-bit
• Package: 64TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 2.5|3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: MA180015 - MODULE PLUG-IN 18F87J10 FOR HPCAC162062 - HEADER INTRFC MPLAB ICD2 64/80PAC164327 - MODULE SKT FOR 64TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F6XJXX/8XJXX
5.2
The checksum is calculated by summing the following:
• The contents of all code memory locations
• The Configuration Block (CFGB), appropriately
• ID locations
The Least Significant 16 bits of this sum are the
checksum.
Table 5-5 (pages 28 through 30) describes how to
calculate the checksum for each device.
TABLE 5-5:
DS39644L-page 28
CFGB80 = Byte sum of [(CW1 & 0CE1h) + (CW2 & 0FC7h) + (CW3 & 01F8h)]
CFGB60 = Byte sum of [(CW1 & 0CE1h) + (CW2 & 0FC7h) + (CW3 & 0100h)]
Legend: Item
masked
Note:
PIC18F85J11
Family
Checksum Computation
SUM(a:b) =
+
CW
CFGB
CW3 address is the last location – 2 of implemented program memory; CW2 is the last location – 4;
CW1 is the last location – 6.
CHECKSUM EQUATION FOR PIC18F6XJXX/8XJXX
=
=
=
PIC18F63J11
PIC18F64J11
PIC18F64J16
PIC18F65J11
PIC18F83J11
PIC18F84J11
PIC18F84J16
PIC18F85J11
Description
Byte sum of locations a to b inclusive (all 3 bytes of code memory)
Addition
Configuration Word
Configuration Block (Masked)
Device
Read Code Protection
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Note:
The checksum calculation differs depend-
ing on the code-protect setting. Since the
code memory locations read out differently
depending on the code-protect setting, the
table describes how to manipulate the
actual code memory values to simulate the
values that would be read from a protected
device. When calculating a checksum by
reading a device, the entire code memory
can simply be read and summed. The
Configuration Word and ID locations can
always be read.
CFGB60 + SUM(0000:1FF7h)
CFGB60 + SUM(0000:3FF7h)
CFGB60 + SUM(0000:5FF7h)
CFGB60 + SUM(0000:7FF7h)
CFGB80 + SUM(0000:1FF7h)
CFGB80 + SUM(0000:3FF7h)
CFGB80 + SUM(0000:5FF7h)
CFGB80 + SUM(0000:7FF7h)
Checksum Computation
 2009 Microchip Technology Inc.
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h