ATTINY44-15MZ Atmel, ATTINY44-15MZ Datasheet - Page 7

• Manufacturer Part Number: ATTINY44-15MZ
• Description: MCU AVR 4K FLASH 15MHZ 20-QFN
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY44-15MZ

• Package / Case: 20-QFN Exposed Pad
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Speed: 16MHz
• Number Of I /o: 12
• Eeprom Size: 256 x 8
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Program Memory Size: 4KB (4K x 8)
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Connectivity: USI
• Core Size: 8-Bit
• Processor Series: ATTINY4x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: SPI, UART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 12
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

5. CPU Core
5.1
5.2
7701E–AVR–02/11
Overview
Architectural Overview
This section discusses the Atmel
CPU core is to ensure correct program execution. The CPU must, therefore, be able to access
memories, perform calculations, control peripherals, and handle interrupts.
Figure 5-1.
In order to maximize performance and parallelism, the AVR
separate memories and buses for program and data. Instructions in the program memory are
executed with a single-level pipelining. While one instruction is being executed, the next
instruction is pre-fetched from the program memory. This concept enables instructions to be
executed in every clock cycle. The program memory is in-system reprogrammable flash
memory.
Control Lines
Instruction
Instruction
Program
Memory
Decoder
Register
Flash
Block Diagram of the AVR Architecture
Atmel ATtiny24/44/84 [Preliminary]
Program
Counter
®
AVR
®
core architecture in general. The main function of the
and Control
EEPROM
Registrers
I/O Lines
Purpose
General
SRAM
Data Bus 8-bit
Status
32 x 8
Data
ALU
®
uses a Harvard architecture, with
Timer/Counter 0
Timer/Counter 1
Serial Interface
Comparator
Watchdog
Universal
Interrupt
Timer
Analog
Unit
7