PIC18F45J10-I/PT Microchip Technology, PIC18F45J10-I/PT Datasheet - Page 26

• Manufacturer Part Number: PIC18F45J10-I/PT
• Description: IC PIC MCU FLASH 16KX16 44TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F45J10-I/PT

• Core Size: 8-Bit
• Program Memory Size: 32KB (16K x 16)
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Number Of I /o: 32
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Controller Family/series: PIC18
• No. Of I/o's: 32
• Ram Memory Size: 1KB
• Cpu Speed: 40MHz
• No. Of Timers: 3
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1024 B
• Interface Type: MSSP, SPI, I2C, EUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Maximum Operating Temperature: + 100 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM163022, DM183040
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 13 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162074 - HEADER INTRFC MPLAB ICD2 44TQFPMA180013 - MODULE PLUG-IN 18F45J10 44TQFPAC162067 - HEADER INTRFC MPLAB ICD2 40/28PAC164330 - MODULE SKT FOR 44TQFP 18F45J10
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC18F2XJXX/4XJXX FAMILY
TABLE 5-7:
DS39687E-page 26
RTCOSC
DSWDTOSC
MSSPMSK
PLLSEL
ADCSEL
IOL1WAY
WPCFG
WPFP<6:0>
WPEND
WPDIS
LS48MHZ
DEV<2:0>
REV<4:0>
DEV<10:3>
Note 1: The Configuration bits can only be programmed indirectly by programming the Flash Configuration Word.
Bit Name
(5)
2: The Configuration bits are reset to ‘1’ only on V
3: These bits are not implemented in PIC18F47J13 family devices.
4: Once this bit is cleared, all the Configuration registers which reside in the last page are also protected. To disable code
5: Not implemented on PIC18F47J53 family devices.
(3)
(1,2)
protection, perform an ICSP™ Bulk Erase operation.
PIC18F47J13 AND PIC18F47J53 FAMILY DEVICES: BIT DESCRIPTIONS (CONTINUED)
Configuration
CONFIG3H
CONFIG3H
CONFIG3H
CONFIG3H
CONFIG4H
CONFIG4H
CONFIG4H
CONFIG3L
CONFIG3L
CONFIG4L
CONFIG4L
DEVID1
DEVID1
DEVID2
Words
RTCC Reference Clock Select bit
1 = RTCC uses T1OSC/T1CKI as reference clock
0 = RTCC uses INTRC as reference clock
DSWDT Reference Clock Select bit
1 = DSWDT uses INTRC as reference clock
0 = DSWDT uses T1OSC/T1CKI as reference clock
MSSP 7-Bit Address Masking Mode Enable bit
1 = 7-Bit Address Masking mode enable
0 = 5-Bit Address Masking mode enable
PLL Selection bit
1 = 4x PLL selected
0 = 96 MHz PLL selected
ADC Mode Selection bit
1 = 10-Bit ADC mode selected
0 = 12-Bit ADC mode selected
IOLOCK Bit One-Way Set Enable bit
1 = The IOLOCK bit (PPSCON<0>) can be set once, provided the unlock sequence has
0 = The IOLOCK bit (PPSCON<0>) can be set and cleared as needed, provided the
Write/Erase Protect Configuration Words Page bit (valid when WPDIS = 0)
1 = Configuration Words page is not erase/write-protected unless WPEND and
0 = Configuration Words page is erase/write-protected, regardless of WPEND and
Write/Erase Protect Page Start/End Location bits
Used with WPEND bit to define which pages in Flash will be write/erase-protected.
Write/Erase Protect Region Select bit (valid when WPDIS = 0)
1 = Flash pages, WPFP<6:0> to Configuration Words page, are write/erase-protected
0 = Flash pages, 0 to WPFP<6:0> are write/erase-protected
Write Protect Disable bit
1 = WPFP<6:0>, WPEND and WPCFG bits ignored; all Flash memory may be erased or
0 = WPFP<6:0>, WPEND and WPCFG bits enabled; write/erase-protect active for the
System Clock Selection bit
1 = System clock is expected at 48 MHz, FS/LS USB CLKEN’s divide-by is set to 8
0 = System clock is expected at 24 MHz, FS/LS USB CLKEN’s divide-by is set to 4
Device ID bits
Used with the DEV<10:3> bits in the Device ID Register 2 to identify the part number.
Revision ID bits
Indicate the device revision.
Device ID bits
Used with the DEV<2:0> bits in the Device ID Register 1 to identify the part number.
been completed. Once set, the Peripheral Pin Select registers cannot be written to a
second time.
unlock sequence has been completed
WPFP<6:0> settings include the Configuration Words page
WPFP<6:0>
written
selected region(s)
DD
Reset; it is reloaded with the programmed value at any device Reset.
Description
© 2009 Microchip Technology Inc.