PIC18F45J10-I/PT Microchip Technology, PIC18F45J10-I/PT Datasheet - Page 10

• Manufacturer Part Number: PIC18F45J10-I/PT
• Description: IC PIC MCU FLASH 16KX16 44TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F45J10-I/PT

• Core Size: 8-Bit
• Program Memory Size: 32KB (16K x 16)
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Number Of I /o: 32
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Controller Family/series: PIC18
• No. Of I/o's: 32
• Ram Memory Size: 1KB
• Cpu Speed: 40MHz
• No. Of Timers: 3
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1024 B
• Interface Type: MSSP, SPI, I2C, EUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Maximum Operating Temperature: + 100 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM163022, DM183040
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 13 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162074 - HEADER INTRFC MPLAB ICD2 44TQFPMA180013 - MODULE PLUG-IN 18F45J10 44TQFPAC162067 - HEADER INTRFC MPLAB ICD2 40/28PAC164330 - MODULE SKT FOR 44TQFP 18F45J10
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC18F2XJXX/4XJXX FAMILY
3.1.2
It is possible to erase one row (1024 bytes of data),
provided
erase/write-protected. Rows are located at static
boundaries beginning at program memory address
000000h, extending to the internal program memory
limit (see Section 2.2 “Memory Maps”).
The Row Erase duration is internally timed. After the
WR bit in EECON1 is set, a NOP is issued, where the
4th PGC is held high for the duration of the Row Erase
time, P10.
The
PIC18F2XJXX/4XJXX family device is shown in
Table 3-2. The flowchart shown in Figure 3-4 depicts the
logic
TABLE 3-2:
FIGURE 3-3:
DS39687E-page 10
Step 1: Enable memory writes.
Step 2: Point to first row in code memory.
Step 3: Enable erase and erase single row.
Step 4: Repeat step 3, with Address Pointer incremented by 1024, until all rows are erased.
Command
PGC
PGD
0000
0000
0000
0000
0000
0000
0000
4-Bit
code
necessary
the
ICSP™ ROW ERASE
1
4-Bit Command
0
2
sequence
0
block
84 A6
6A F8
6A F7
6A F6
88 A6
82 A6
00 00
ERASE CODE MEMORY CODE SEQUENCE
3
0
Data Payload
SET WR AND START ROW ERASE TIMING
to
4
0
is
P5
completely
not
to
1
0
2
code-protected
1
Row
3
16-Bit Data Payload
BSF
CLRF
CLRF
CLRF
BSF
BSF
NOP – hold PGC high for time P10.
1
4
0
Erase
erase
5
EECON1, WREN
TBLPTRU
TBLPTRH
TBLPTRL
EECON1, FREE
EECON1, WR
0
6
1
PGD = Input
or
a
a
15
0
16
1
P5A
PIC18F2XJXX/4XJXX
diagram that details the “Row Erase” command and
parameter P10 is shown in Figure 3-6.
4-Bit Command
1
Note 1: If the last row of program memory is
0
2
Core Instruction
0
2: The TBLPTR register can point at any
3: If code protection has been enabled,
3
0
erased, bit 3 of CONFIG1H must also be
programmed as ‘0’.
byte within the row intended for erase.
ICSP Bulk Erase (all program memory
erased) operations can be used to dis-
able code protection. ICSP Row Erase
operations cannot be used to disable
code protection.
0
Row-Erase Time
P10
© 2009 Microchip Technology Inc.
family
device.
4
P5
Data Payload
1
The
0
16-Bit
2
0
timing
3
0