TINY88-15MZ Atmel, TINY88-15MZ Datasheet - Page 214

• Manufacturer Part Number: TINY88-15MZ
• Description: MCU AVR 8KB FLASH 12MHZ 32-QFN
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of TINY88-15MZ

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 28
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 64 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 21-3. 2-wire Serial Bus Timing
21.8
214
SCL
SDA
4. f
5. This requirement applies to all 2-wire serial interface operation in ATtiny88. Other devices connected to the 2-wire serial bus
6. The actual low period generated by the 2-wire serial interface of ATtiny88 is (1/f
7. The actual low period generated by the 2-wire serial interface of ATtiny88 is (1/f
SPI Characteristics
t
ATtiny88 Automotive
SU;STA
need only obey the general f
MHz for the low time requirement to be strictly met at f
not be strictly met for f
speed (400 kHz) with other ATtiny88 devices, as well as any other device with a proper t
CK
= CPU clock frequency
See
Table 21-8.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
SCL
Figure 21-4
t
HD;STA
Description
SCK period
SCK high/low
Rise/Fall time
Setup
Hold
Out to SCK
SCK to out
SCK to out high
SS low to out
SCK period
SCK high/low
Rise/Fall time
Setup
Hold
SCK to out
SCK to SS high
SS high to tri-state
SS low to SCK
> 308 kHz when f
t
t
of
LOW
SCL
requirement.
SPI Timing Parameters
and
(1)
Figure 21-5
t
HIGH
CK
t
HD;DAT
= 8 MHz. Still, ATtiny88 devices connected to the bus may communicate at full
Mode
Master
Master
Master
Master
Master
Master
Master
Master
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Slave
for details.
SCL
t
LOW
= 100 kHz.
Min
4 • t
2 • t
10
t
20
20
ck
ck
ck
t
SU;DAT
SCL
SCL
Typ
See
50% duty cycle
3.6
10
10
0.5 • t
10
10
15
15
10
- 2/f
- 2/f
CK
Table 14-5
CK
sck
), thus the low time requirement will
LOW
), thus f
acceptance margin.
CK
t
SU;STO
must be greater than 6
Max
1600
t
r
9157B–AVR–01/10
t
BUF
ns