PIC12CE519-04/P Microchip Technology, PIC12CE519-04/P Datasheet - Page 150

• Manufacturer Part Number: PIC12CE519-04/P
• Description: IC MCU OTP 1KX12 W/EE 8DIP
• Manufacturer: Microchip Technology
• Series: PIC® 12Cr

Specifications of PIC12CE519-04/P

• Program Memory Type: OTP
• Program Memory Size: 1.5KB (1K x 12)
• Package / Case: 8-DIP (0.300", 7.62mm)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 4MHz
• Peripherals: POR, WDT
• Number Of I /o: 5
• Eeprom Size: 16 x 8
• Ram Size: 41 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Processor Series: PIC12C
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 41 B
• Maximum Clock Frequency: 4 MHz
• Number Of Programmable I/os: 5
• Number Of Timers: 1
• Operating Supply Voltage: 3 V to 5.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: ICE2000
• Minimum Operating Temperature: 0 C
• On-chip Adc: 8 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: ISPICR1 - ADAPTER IN-CIRCUIT PROGRAMMINGDVA12XP080 - ADAPTER DEVICE FOR MPLAB-ICEAC124001 - MODULE SKT PROMATEII 8DIP/SOIC
• Data Converters: -
• Connectivity: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PICmicro MID-RANGE MCU FAMILY
9.6
DS31009A-page 9-10
PORTE and the TRISE Register
PORTE can be up to an 8-bit port with Schmitt Trigger input buffers. Each pin is individually con-
figurable as an input or output.
Example 9-5: Initializing PORTE
Figure 9-8: Typical PORTE Block Diagram (in I/O Port Mode)
Data Bus
WR PORT
WR TRIS
RD PORT
Note: I/O pins have protection diodes to V
Note:
CLRF
CLRF
BSF
MOVLW
MOVWF
On some devices with PORTE, the upper bits of the TRISE register are used for the
Parallel Slave Port control and status bits.
STATUS
PORTE
STATUS, RP0
0x03
TRISE
TRIS Latch
Data Latch
D
D
CK
CK
; Bank0
; Initialize PORTE by clearing output
;
; Select Bank1
; Value used to initialize data direction
; PORTE<1:0> = inputs, PORTE<7:2> = outputs
Q
Q
Q
Q
RD TRIS
data latches
DD
and V
SS
.
Q
EN
D
1997 Microchip Technology Inc.
Schmitt
Trigger
input
buffer
I/O pin