ATTINY88-MUR Atmel, ATTINY88-MUR Datasheet - Page 153
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ATTINY88-MUR
Manufacturer Part Number
ATTINY88-MUR
Description
MCU AVR 8KB FLASH 12MHZ 32QFN
Manufacturer
Atmel
Series
AVR® ATtinyr
Datasheet
1.ATTINY48-MU.pdf
(302 pages)
Specifications of ATTINY88-MUR
Core Processor
AVR
Core Size
8-Bit
Speed
12MHz
Connectivity
I²C, SPI
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
28
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
64 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATTINY88-MUR
Manufacturer:
AT
Quantity:
20 000
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15.8.5
Table 15-6.
8008G–AVR–04/11
Status Code
(TWSR)
Prescaler Bits
are 0
0xF8
0x00
Miscellaneous States
Status of the 2-wire Serial Bus
and 2-wire Serial Interface
Hardware
No relevant state information
available; TWINT = “0”
Bus error due to an illegal
START or STOP condition
Miscellaneous States
Figure 15-18. Formats and States in the Slave Transmitter Mode
There are two status codes that do not correspond to a defined TWI state, see
Status 0xF8 indicates that no relevant information is available because the TWINT Flag is not
set. This occurs between other states, and when the TWI is not involved in a serial transfer.
Status 0x00 indicates that a bus error has occurred during a 2-wire Serial Bus transfer. A bus
error occurs when a START or STOP condition occurs at an illegal position in the format frame.
Examples of such illegal positions are during the serial transfer of an address byte, a data byte,
or an acknowledge bit. When a bus error occurs, TWINT is set. To recover from a bus error, the
TWSTO Flag must set and TWINT must be cleared by writing a logic one to it. This causes the
TWI to enter the not addressed Slave mode and to clear the TWSTO Flag (no other bits in
TWCR are affected). The SDA and SCL lines are released, and no STOP condition is
transmitted.
Reception of the own
slave address and one or
more data bytes
Arbitration lost as master
and addressed as slave
Last data byte transmitted.
Switched to not addressed
slave (TWEA = '0')
From master to slave
From slave to master
To/from TWDR
No TWDR action
No TWDR action
S
Application Software Response
SLA
STA
0
R
No TWCR action
STO
DATA
1
To TWCR
$A8
$B0
A
A
TWIN
n
T
1
A
TWE
A
X
DATA
Any number of data bytes
and their associated acknowledge bits
This number (contained in TWSR) corresponds
to a defined state of the 2-Wire Serial Bus. The
prescaler bits are zero or masked to zero
Next Action Taken by TWI Hardware
Only the internal hardware is affected, no STOP condi-
tion is sent on the bus. In all cases, the bus is released
and TWSTO is cleared.
Wait or proceed current transfer
$B8
A
DATA
ATtiny48/88
$C0
$C8
A
A
Table
P or S
All 1's
15-6.
P or S
153
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