ATTINY13V-10SUR Atmel, ATTINY13V-10SUR Datasheet
ATTINY13V-10SUR
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ATTINY13V-10SUR Summary of contents
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... Operating Voltage: – 1.8 - 5.5V for ATtiny13V – 2.7 - 5.5V for ATtiny13 • Speed Grade – ATtiny13V MHz @ 1.8 - 5.5V MHz @ 2.7 - 5.5V – ATtiny13 MHz @ 2.7 - 5.5V MHz @ 4.5 - 5.5V • Industrial Temperature Range • Low Power Consumption – Active Mode: • ...
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... Pin Configurations Figure 1-1. Pinout ATtiny13/ATtiny13V (PCINT5/RESET/ADC0/dW) PB5 (PCINT3/CLKI/ADC3) PB3 (PCINT4/ADC2) PB4 (PCINT5/RESET/ADC0/dW) PB5 (PCINT3/CLKI/ADC3) PB3 (PCINT4/ADC2) PB4 NOTE: Bottom pad should be soldered to ground. DNC: Do Not Connect (PCINT5/RESET/ADC0/dW) PB5 (PCINT3/CLKI/ADC3) PB3 (PCINT4/ADC2) PB4 NOTE: Bottom pad should be soldered to ground. DNC: Do Not Connect ...
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Pin Descriptions 1.1.1 VCC Digital supply voltage. 1.1.2 GND Ground. 1.1.3 Port B (PB5:PB0) Port 6-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics ...
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Overview The ATtiny13 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny13 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to ...
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... Hardware Reset. The ADC Noise Reduction mode stops the CPU and all I/O modules except ADC, to minimize switching noise during ADC conversions. The device is manufactured using Atmel’s high density non-volatile memory technology. The On-chip ISP Flash allows the Program memory to be re-programmed In-System through an SPI serial interface conventional non-volatile memory programmer On-chip boot code running on the AVR core ...
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... General Information 3.1 Resources A comprehensive set of drivers, application notes, data sheets and descriptions on development tools are available for download at http://www.atmel.com/avr. 3.2 Code Examples This documentation contains simple code examples that briefly show how to use various parts of the device. These code examples assume that the part specific header file is included before compilation ...
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CPU Core This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle ...
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The fast-access Register File contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation typ- ical ALU operation, two operands are output from the Register ...
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SREG – Status Register Bit Read/Write Initial Value • Bit 7 – I: Global Interrupt Enable The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual inter- rupt enable control is then performed ...
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General Purpose Register File The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve the required performance and flexibility, the following input/output schemes are supported by the Register File: • One 8-bit output ...
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Figure 4-3. X-register Y-register Z-register In the different addressing modes these address registers have functions as fixed displacement, automatic increment, and automatic decrement (see the instruction set reference for details). 4.5 Stack Pointer The Stack is mainly used for storing ...
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Instruction Execution Timing This section describes the general access timing concepts for instruction execution. The AVR CPU is driven by the CPU clock clk chip. No internal clock division is used. Figure 4-4 on page 12 by the Harvard ...
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RESET has the highest priority, and next is INT0 – the External Interrupt Request 0. When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are dis- abled. The user software can write logic ...
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When using the SEI instruction to enable interrupts, the instruction following SEI will be exe- cuted before any pending interrupts, as shown in this example. Assembly Code Example sei sleep; enter sleep, waiting for interrupt ; note: will enter sleep ...
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Memories This section describes the different memories in the ATtiny13. The AVR architecture has two main memory spaces, the Data memory and the Program memory space. In addition, the ATtiny13 features an EEPROM Memory for data storage. All three ...
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The 32 general purpose working registers, 64 I/O Registers, and the 64 bytes of internal data SRAM in the ATtiny13 are all accessible through all these addressing modes. The Register File is described in Figure 5-2. 5.2.1 Data Memory Access ...
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The write access times for the EEPROM are given in tion, however, lets the user software detect when the next byte can be written. If the user code contains instructions that write the EEPROM, some precautions must be taken. In ...
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The following code examples show one assembly and one C function for erase, write, or atomic write of the EEPROM. The examples assume that interrupts are controlled (e.g., by disabling interrupts globally) so that no interrupts will occur during execution ...
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The next code examples show assembly and C functions for reading the EEPROM. The exam- ples assume that interrupts are controlled so that no interrupts will occur during execution of these functions. Assembly Code Example EEPROM_read: C Code Example unsigned ...
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I/O Memory The I/O space definition of the ATtiny13 is shown in All ATtiny13 I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the ...
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EECR – EEPROM Control Register Bit Read/Write Initial Value • Bit 7 – Res: Reserved Bit This bit is reserved for future use and will always read ATtiny13. For compatibility with future AVR devices, always write ...
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Bit 0 – EERE: EEPROM Read Enable The EEPROM Read Enable Signal – EERE – is the read strobe to the EEPROM. When the cor- rect address is set up in the EEARL Register, the EERE bit must be ...
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System Clock and Clock Options 6.1 Clock Systems and their Distribution Figure 6-1 need not be active at a given time. In order to reduce power consumption, the clocks to modules not being used can be halted by using ...
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ADC Clock – clk ADC The ADC is provided with a dedicated clock domain. This allows halting the CPU and I/O clocks in order to reduce noise generated by digital circuitry. This gives more accurate ADC conversion results. 6.2 ...
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When this clock source is selected, start-up times are determined by the SUT fuses as shown in Table 6-3. Table 6-3. SUT1.. When applying an external clock required to avoid sudden changes in the ...
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When this Oscillator is selected, start-up times are determined by the SUT fuses as shown in Table 6-5. Table 6-5. SUT1.. ( Note: 6.2.3 Internal 128 kHz Oscillator The 128 kHz internal Oscillator is a low ...
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The ripple counter that implements the prescaler runs at the frequency of the undivided clock, which may be faster than the CPU’s clock frequency. Hence not possible to determine the state of the prescaler – even if it ...
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CLKPR – Clock Prescale Register Bit Read/Write Initial Value • Bit 7 – CLKPCE: Clock Prescaler Change Enable The CLKPCE bit must be written to logic one to enable change of the CLKPS bits. The CLKPCE bit is only ...
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Table 6-8. CLKPS3 2535J–AVR–08/10 Clock Prescaler Select (Continued) CLKPS2 CLKPS1 CLKPS0 Clock Division Factor 1 Reserved 0 Reserved 1 ...
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Power Management and Sleep Modes The high performance and industry leading code efficiency makes the AVR microcontrollers an ideal choise for low power applications. In addition, sleep modes enable the application to shut down unused modules in the MCU, ...
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Control and Status Register – ACSR. This will reduce power consumption in Idle mode. If the ADC is enabled, a conversion starts automatically when this mode is entered. 7.1.2 ADC Noise Reduction Mode When the SM[1:0] bits are written to ...
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Internal Voltage Reference The Internal Voltage Reference will be enabled when needed by the Brown-out Detection, the Analog Comparator or the ADC. If these modules are disabled as described in the sections above, the internal voltage reference will be ...
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Bits 4:3 – SM[1:0]: Sleep Mode Select Bits 1:0 These bits select between the three available sleep modes as shown in Table 7-2. • Bit 2 – Res: Reserved Bit This bit is a reserved bit in the ATtiny13 ...
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System Control and Reset 8.0.1 Resetting the AVR During reset, all I/O Registers are set to their initial values, and the program starts execution from the Reset Vector. The instruction placed at the Reset Vector must be a RJMP ...
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Reset Sources The ATtiny13 has four sources of reset: • Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset threshold (V • External Reset. The MCU is reset when a low level is ...
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External Reset An External Reset is generated by a low level on the RESET pin if enabled. Reset pulses longer than the minimum pulse width erate a reset, even if the clock is not running. Shorter pulses are not ...
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Watchdog Reset When the Watchdog times out, it will generate a short reset pulse of one CK cycle duration. On the falling edge of this pulse, the delay timer starts counting the Time-out period t “Interrupts” on page 44 ...
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If the system doesn't restart the counter, an interrupt or system reset will be issued. Figure 8-7. In Interrupt mode, the WDT gives an interrupt when the timer expires. This interrupt can be used to wake the ...
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The following code example shows one assembly and one C function for turning off the Watch- dog Timer. The example assumes that interrupts are controlled (e.g. by disabling interrupts globally) so that no interrupts will occur during the execution of ...
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Watchdog System Reset Flag (WDRF) and the WDE control bit in the initialisation routine, even if the Watchdog is not in use. The following code example shows one assembly and one C ...
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Register Description 8.4.1 MCUSR – MCU Status Register The MCU Status Register provides information on which reset source caused an MCU Reset. Bit Read/Write Initial Value • Bits 7:4 – Res: Reserved Bits These bits are reserved bits in ...
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This is useful for keeping the Watchdog Timer security while using the interrupt. To stay in Inter- rupt and System Reset Mode, WDTIE must be set after each interrupt. This should however not be done within the interrupt service routine ...
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Table 8-2. WDP3 2535J–AVR–08/10 Watchdog Timer Prescale Select Number of WDT Oscillator WDP2 WDP1 WDP0 Typical ...
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Interrupts This section describes the specifics of the interrupt handling as performed in ATtiny13. For a general explanation of the AVR interrupt handling, refer to page 12. 9.1 Interrupt Vectors The interrupt vectors of ATtiny13 are described in Table ...
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External Interrupts The External Interrupts are triggered by the INT0 pin or any of the PCINT5..0 pins. Observe that, if enabled, the interrupts will trigger even if the INT0 or PCINT5..0 pins are configured as out- puts. This feature ...
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Register Description 9.3.1 MCUCR – MCU Control Register The External Interrupt Control Register A contains control bits for interrupt sense control. Bit Read/Write Initial Value • Bits 1, 0 – ISC01, ISC00: Interrupt Sense Control 0 Bit 1 and ...
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GIFR – General Interrupt Flag Register Bit Read/Write Initial Value • Bits 7, 4:0 – Res: Reserved Bits These bits are reserved bits in the ATtiny13 and will always read as zero. • Bit 6 – INTF0: External Interrupt ...
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I/O Ports 10.1 Overview All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin ...
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Note that enabling the alternate function of some of the port pins does not affect the use of the other pins in the port as general digital I/O. 10.2 Ports as General Digital I/O The ports are bi-directional I/O ports ...
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If PORTxn is written logic one when the pin is configured as an input pin, the pull-up resistor is activated. To switch the pull-up resistor off, PORTxn has to be written logic zero or the pin has to be configured ...
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Figure 10-3. Synchronization when Reading an Externally Applied Pin value SYSTEM CLK INSTRUCTIONS SYNC LATCH Consider the clock period starting shortly after the first falling edge of the system clock. The latch is closed when the clock is low, and ...
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The following code example shows how to set port B pins 0 and 1 high, 2 and 3 low, and define the port pins from input with a pull-up assigned to port pin 4. The resulting ...
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Sleep mode, as the clamping in these sleep mode produces the requested logic change. 10.2.6 Unconnected Pins If some pins are unused recommended to ensure that these pins have a defined level. Even though most of ...
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The overriding signals may not be present in all port pins, but description applicable to all port pins in the AVR microcontroller family. Table 10-2 on page 54 indexes from signals are generated internally in the modules having the alternate ...
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Table 10-3. Table 10-4 shown in Table 10-4. Signal PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO Note: 2535J–AVR–08/10 Port B Pins Alternate Functions Port Pin Alternate Function RESET: Reset Pin dW: debugWIRE I/O PB5 ADC0: ADC ...
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Table 10-5. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO 10.4 Register Description 10.4.1 MCUCR – MCU Control Register Bit Read/Write Initial Value • Bits 7, 2– Res: Reserved Bits These bits are reserved bits ...
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PINB – Port B Input Pins Address Bit Read/Write Initial Value 2535J–AVR–08/ – – PINB5 PINB4 R R R/W R N/A N PINB3 PINB2 PINB1 PINB0 R/W R/W R/W ...
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... I/O Registers, including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed in the Figure 11-1. 8-bit Timer/Counter Block Diagram ATtiny13 58 “Pinout ATtiny13/ATtiny13V” on page “Register Description” on page Count Clear Control Logic ...
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Registers The Timer/Counter (TCNT0) and Output Compare Registers (OCR0A and OCR0B) are 8-bit registers. Interrupt request (abbreviated to Int.Req. in the figure) signals are all visible in the Timer Interrupt Flag Register (TIFR0). All interrupts are individually masked with ...
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Figure 11-2. Counter Unit Block Diagram Signal description (internal signals): count direction clear clk top bottom Depending of the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clk selected by the Clock Select ...
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Figure 11-3. Output Compare Unit, Block Diagram The OCR0x Registers are double buffered when using any of the Pulse Width Modulation (PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the dou- ble buffering is ...
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Similarly, do not write the TCNT0 value equal to BOTTOM when the counter is down-counting. The setup of the OC0x should be performed before setting the Data Direction Register for the port pin to output. The easiest way of ...
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The design of the Output Compare pin logic allows initialization of the OC0x state before the out- put is enabled. Note that some COM0x1:0 bit settings are reserved for certain modes of operation. 11.6.1 Compare Output Mode and Waveform Generation ...
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The timing diagram for the CTC mode is shown in (TCNT0) increases until a Compare Match occurs between TCNT0 and OCR0A, and then coun- ter (TCNT0) is cleared. Figure 11-5. CTC Mode, Timing Diagram TCNTn OCn (Toggle) Period An interrupt ...
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DAC applications. High frequency allows physically small sized external components (coils, capacitors), and therefore reduces total system cost. In fast PWM mode, the counter is incremented until the counter value matches the TOP value. The ...
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COM0A1:0 bits.) A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by set- ting OC0x to toggle ...
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The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches BOTTOM. The Interrupt Flag can be used to generate an interrupt each time the counter reaches the BOTTOM value. In phase correct PWM mode, the compare unit allows ...
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Figure 11-8. Timer/Counter Timing Diagram, no Prescaling clk I/O clk Tn (clk /1) I/O TCNTn TOVn Figure 11-9 Figure 11-9. Timer/Counter Timing Diagram, with Prescaler (f clk I/O clk Tn (clk /8) I/O TCNTn TOVn Figure 11-10 mode and PWM ...
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Figure 11-11. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Pres- clk I/O clk Tn (clk /8) I/O TCNTn (CTC) OCRnx OCFnx 11.9 Register Description 11.9.1 TCCR0A – Timer/Counter Control Register A Bit Read/Write Initial Value • Bits ...
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Table 11-3. COM01 Note: Table 11-4 rect PWM mode. Table 11-4. COM0A1 Note: • Bits 5:4 – COM0B1:0: Compare Match Output B Mode These bits control the Output Compare pin (OC0B) behavior. ...
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Table 11-5. COM01 Table 11-6 mode. Table 11-6. COM01 Note: Table 11-7 rect PWM mode. Table 11-7. COM0A1 Note: • Bits 3, 2 – Res: Reserved Bits These ...
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Bits 1:0 – WGM01:0: Waveform Generation Mode Combined with the WGM02 bit found in the TCCR0B Register, these bits control the counting sequence of the counter, the source for maximum (TOP) counter value, and what type of wave- form ...
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Bit 6 – FOC0B: Force Output Compare B The FOC0B bit is only active when the WGM bits specify a non-PWM mode. However, for ensuring compatibility with future devices, this bit must be set to zero when TCCR0B is ...
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OCR0A – Output Compare Register A Bit Read/Write Initial Value The Output Compare Register A contains an 8-bit value that is continuously compared with the counter value (TCNT0). A match can be used to generate an Output Compare interrupt, ...
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TIFR0 – Timer/Counter 0 Interrupt Flag Register Bit Read/Write Initial Value • Bits 7:4, 0 – Res: Reserved Bits These bits are reserved bits in the ATtiny13 and will always read as zero. • Bit 3 – OCF0B: Output ...
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Timer/Counter Prescaler 12.1 Overview The Timer/Counter can be clocked directly by the system clock (by setting the CSn2:0 = 1). This provides the fastest operation, with a maximum Timer/Counter clock frequency equal to system clock frequency (f clock source. ...
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However, due to variation of the system clock frequency and duty cycle caused by Oscillator source (crystal, resonator, and capacitors) ...
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Analog Comparator The Analog Comparator compares the input values on the positive pin AIN0 and negative pin AIN1. When the voltage on the positive pin AIN0 is higher than the voltage on the negative pin AIN1, the Analog Comparator ...
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Register Description 13.2.1 ADCSRB – ADC Control and Status Register Bit Read/Write Initial Value • Bit 6 – ACME: Analog Comparator Multiplexer Enable When this bit is written logic one and the ADC is switched off (ADEN in ADCSRA ...
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Bits 1, 0 – ACIS1, ACIS0: Analog Comparator Interrupt Mode Select These bits determine which comparator events that trigger the Analog Comparator interrupt. The different settings are shown in Table 13-2. ACIS1 When changing the ...
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Analog to Digital Converter 14.1 Features • 10-bit Resolution • 0.5 LSB Integral Non-linearity • ± 2 LSB Absolute Accuracy • 260 µs Conversion Time • kSPS at Maximum Resolution • Four Multiplexed Single ...
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The ADC is connected to a 4-channel Analog Multiplexer which allows four single-ended voltage inputs constructed from the pins of Port B. The single-ended voltage inputs refer to 0V (GND). The ADC contains a Sample and Hold circuit which ensures ...
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Figure 14-2. ADC Auto Trigger Logic Using the ADC Interrupt Flag as a trigger source makes the ADC start a new conversion as soon as the ongoing conversion has finished. The ADC then operates in Free Running mode, con- stantly ...
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The prescaler starts counting from the moment the ADC is switched on by setting the ADEN bit in ADCSRA. The prescaler keeps running for as long as the ADEN bit is set, and is continuously reset when ADEN is low. ...
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When Auto Triggering is used, the prescaler is reset when the trigger event occurs, as shown in Figure 14-6 this mode, the sample-and-hold takes place two ADC clock cycles after the rising edge on the trigger source signal. Three additional ...
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For a summary of conversion times, see Table 14-1. Condition First conversion Normal conversions Auto Triggered conversions 14.6 Changing Channel or Reference Selection The MUXn and REFS1:0 bits in the ADMUX Register are single buffered through a temporary register to ...
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ADC Voltage Reference The reference voltage for the ADC (V ended channels that exceed V either V voltage source may be inaccurate, and the user is advised to discard this result. 14.7 ADC Noise Canceler The ADC features a ...
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The ADC is optimized for analog signals with an output impedance of approximately 10 kΩ or less. If such a source is used, the sampling time will be negligible source with higher imped- ance is used, the sampling ...
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Offset: The deviation of the first transition (0x000 to 0x001) compared to the ideal transition (at 0.5 LSB). Ideal value: 0 LSB. Figure 14-9. Offset Error Output Code • Gain Error: After adjusting for offset, the Gain Error is ...
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Integral Non-linearity (INL): After adjusting for offset and gain error, the INL is the maximum deviation of an actual transition compared to an ideal transition for any code. Ideal value: 0 LSB. Figure 14-11. Integral Non-linearity (INL) Output Code ...
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Quantization Error: Due to the quantization of the input voltage into a finite number of codes, a range of input voltages (1 LSB wide) will code to the same value. Always ± 0.5 LSB. • Absolute Accuracy: The maximum ...
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Bits 4:2 – Res: Reserved Bits These bits are reserved bits in the ATtiny13 and will always read as zero. • Bits 1:0 – MUX1:0: Analog Channel Selection Bits The value of these bits selects which combination of analog ...
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Bit 3 – ADIE: ADC Interrupt Enable When this bit is written to one and the I-bit in SREG is set, the ADC Conversion Complete Inter- rupt is activated. • Bits 2:0 – ADPS2:0: ADC Prescaler Select Bits These ...
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The ADLAR bit in ADMUX, and the MUXn bits in ADMUX affect the way the result is read from the registers. If ADLAR is set, the result is left adjusted. If ADLAR is cleared (default), the result is right adjusted. ...
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On-chip Debug System 15.1 Features • Complete Program Flow Control • Emulates All On-chip Functions, Both Digital and Analog, except RESET Pin • Real-time Operation • Symbolic Debugging Support (Both at C and Assembler Source Level, or for ...
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When designing a system where debugWIRE will be used, the following must be observed: • Pull-Up resistor on the dW/(RESET) line must be in the range of 10k to 20 kΩ. However, the pull-up resistor is optional. • Connecting the ...
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Self-Programming the Flash The device provides a Self-Programming mechanism for downloading and uploading program code by the MCU itself. The Self-Programming can use any available data interface and associ- ated protocol to read code and write (program) that code ...
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If the EEPROM is written in the middle of an SPM Page Load operation, all data loaded will be lost. 16.3 Performing a Page Write To execute Page Write, set up the address in the Z-pointer, write “00000101” to SPMCSR ...
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The LPM instruction uses the Z-pointer to store the address. Since this instruction addresses the Flash byte-by-byte, also the LSB (bit Z0) of the Z-pointer is used. 16.5 EEPROM Write Prevents Writing to SPMCSR Note that an EEPROM write operation ...
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To read the Fuse High Byte (FHB), simply replace the address in the Z-pointer with 0x0003 and repeat the procedure above. If successful, the contents of the destination register are as follows. Bit Rd See sections for more information on ...
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Register Description 16.9.1 SPMCSR – Store Program Memory Control and Status Register The Store Program Memory Control and Status Register contains the control bits needed to con- trol the Program memory operations. Bit Read/Write Initial Value • Bits 7..5 ...
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Memory Programming This section describes how ATtiny13 memories can be programmed. 17.1 Program And Data Memory Lock Bits ATtiny13 provides two lock bits which can be left unprogrammed (“1”) or can be programmed (“0”) to obtain the additional security ...
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Fuse Bytes The ATtiny13 has two fuse bytes. briefly the functionality of all the fuses and how they are mapped into the fuse bytes. Note that the fuses are read as logical zero, “0”, if they are programmed. Table ...
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... Signature Bytes All Atmel microcontrollers have a three-byte signature code which identifies the device. This code can be read in both serial and high-voltage programming mode, even when the device is locked. The three bytes reside in a separate address space. ...
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Serial Programming Both the Flash and EEPROM memory arrays can be programmed using the serial SPI bus while RESET is pulled to GND. The serial interface consists of pins SCK, MOSI (input) and MISO (out- put). See Figure 17-1. ...
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Serial Programming Algorithm When writing serial data to the ATtiny13, data is clocked on the rising edge of SCK. When reading data from the ATtiny13, data is clocked on the falling edge of SCK. See 18-5 on page 121 ...
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Table 17-8. Symbol t WD_FLASH t WD_EEPROM t WD_ERASE t WD_FUSE 17.6.2 Serial Programming Instruction set The instruction set is described in Table 17-9. Serial Programming Instruction Set Instruction Byte 1 Programming Enable 1010 1100 Chip Erase 1010 1100 ...
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Table 17-9. Serial Programming Instruction Set (Continued) Instruction Byte 1 Read Fuse Byte 0101 H000 Write Fuse Byte 1010 1100 Read Signature Byte 0011 0000 Read Calibration Byte 0011 1000 Poll RDY/BSY 1111 0000 Note address high bits, ...
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Table 17-10. Pin Name Mapping Signal Name in High-voltage Serial Programming Mode SDI SII SDO SCI The minimum period for the Serial Clock Input (SCI) during High-voltage Serial Programming is 220 ns. Table 17-11. Pin Values Used to Enter Programming ...
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Wait until Vcc actually reaches 4.5 - 5.5V before giving any serialinstructions on SDI/SII. 7. Exit Programming mode by power the device down or by bringing RESET pin to 0V. Table 17-12. High-voltage Reset Characteristics Supply Voltage V CC ...
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Table 17-13. High-Voltage Serial Programming Instruction Set for ATtiny13 (Continued) Instruction Instr.1/5 SDI 0_00bb_bbbb_00 Load EEPROM SII 0_0000_1100_00 Page Buffer SDO x_xxxx_xxxx_xx SDI 0_0000_0000_00 Program SII 0_0110_0100_00 EEPROM Page SDO x_xxxx_xxxx_xx SDI 0_00bb_bbbb_00 SII 0_0000_1100_00 SDO x_xxxx_xxxx_xx Write EEPROM Byte ...
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Table 17-13. High-Voltage Serial Programming Instruction Set for ATtiny13 (Continued) Instruction Instr.1/5 SDI 0_0000_1000_00 Read Signature SII 0_0100_1100_00 Bytes SDO x_xxxx_xxxx_xx SDI 0_0000_1000_00 Read SII 0_0100_1100_00 Calibration Byte SDO x_xxxx_xxxx_xx SDI 0_0000_0000_00 Load “No Operation” SII 0_0100_1100_00 Command SDO x_xxxx_xxxx_xx ...
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Programming the Flash The Flash is organized in pages, see the program data is latched into a page buffer. This allows one page of program data to be pro- grammed simultaneously. The following procedure describes how to program the ...
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Figure 17-4. High-voltage Serial Programming Waveforms SDI PB0 SII PB1 SDO PB2 SCI PB3 17.8.3 Programming the EEPROM The EEPROM is organized in pages, see EEPROM, the data is latched into a page buffer. This allows one page of data ...
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Reading the Signature Bytes and Calibration Byte The algorithms for reading the Signature bytes and Calibration byte are shown in page 110. 17.8.8 Power-off sequence Set SCI to “0”. Set RESET to “1”. Turn V 18. Electrical Characteristics 18.1 ...
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Table 18-1. DC Characteristics, T Symbol Parameter Input Leakage I LIH Current I/O Pin Pull-Up Resistor, I/O Pin R PU Pull-Up Resistor, Reset Pin Supply Current, Active Mode I Supply Current, CC Idle Mode Supply Current, Power-Down Mode Notes: 1. ...
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... Figure 18-2. Maximum Frequency vs. V 2535J–AVR–08/10 18-2, the maximum frequency vs. V < 4.5V MHz 1.8V 20 MHz 10 MHz 2.7V As shown in CC. relationship is linear between 1.8V < for ATtiny13V CC Safe Operating Area 2.7V for ATtiny13 CC Safe Operating Area 4.5V 5.5V Figure 18-1 and < 2.7V CC 5.5V ...
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... Figure 19-53 on page 150 Fixed voltage within: (2) 1.8V – 5.5V (3) 2.7V – 5.5V 1. Accuracy of oscillator frequency at calibration point (fixed temperature and fixed voltage). 2. Voltage range for ATtiny13V. 3. Voltage range for ATtiny13. V IH1 V IL1 V = 1.8 - 5.5V CC Min. 0 250 100 100 ...
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System and Reset Characteristics Table 18-4. Reset, Brown-out and Internal Voltage Reference Characteristics Symbol Parameter Power-on Reset Threshold Voltage (rising) V Power-on Reset Threshold Voltage POT (1) (falling) V RESET Pin Threshold Voltage RST t Minimum pulse width on ...
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ADC Characteristics Table 18-7. ADC Characteristics, Single Ended Channels. T Symbol Parameter Resolution Absolute accuracy (Including INL, DNL, and Quantization, Gain and Offset Errors) Integral Non-Linearity (INL) (Accuracy after Offset and Gain Calibration) Differential Non-linearity (DNL) Gain Error Offset ...
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... MISO MSB (MOSI) MSB (MISO) (SCK) SAMPLE Serial Programming Characteristics, T (Unless Otherwise Noted) Parameter Oscillator Frequency (ATtiny13V, V Oscillator Period (ATtiny13V Oscillator Frequency (ATtiny13, V Oscillator Period (ATtiny13 2.7 - 5.5V) CC Oscillator Frequency (ATtiny13, V Oscillator Period (ATtiny13 4.5V - 5.5V) CC SCK Pulse Width High SCK Pulse Width Low ...
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High-voltage Serial Programming Characteristics Figure 18-6. High-voltage Serial Programming Timing SDI (PB0), SII (PB1) Table 18-9. Symbol t SHSL t SLSH t IVSH t SHIX t SHOV t WLWH_PFB ATtiny13 122 t IVSH SCI (PB3) SDO (PB2) High-voltage Serial ...
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Typical Characteristics The data contained in this section is largely based on simulations and characterization of similar devices in the same process and design methods. Thus, the data should be treated as indica- tions of how the part will ...
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Figure 19-2. Active Supply Current vs. Frequency ( MHz) Figure 19-3. Active Supply Current vs. V ATtiny13 124 ACTIVE SUPPLY CURRENT vs. FREQUENCY 1 ...
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Figure 19-4. Active Supply Current vs. V Figure 19-5. Active Supply Current vs. V 0.14 0.12 0.08 0.06 0.04 0.02 2535J–AVR–08/10 ACTIVE SUPPLY CURRENT vs. V INTERNAL RC OSCILLATOR, 4.8 MH 4.5 4 3.5 3 2.5 2 1.5 1 0.5 ...
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Figure 19-6. Active Supply Current vs. V 0.04 0.035 0.03 0.025 0.02 0.015 0.01 0.005 19.2 Idle Supply Current Figure 19-7. Idle Supply Current vs. Frequency (0.1 - 1.0 MHz) 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 ATtiny13 ...
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Figure 19-8. Idle Supply Current vs. Frequency ( MHz) Figure 19-9. Idle Supply Current vs. V 2535J–AVR–08/10 IDLE SUPPLY CURRENT vs. FREQUENCY 1 - 20MHz 5 4.5 4 3.5 3 2.5 2 1.5 1 0.5 1 ...
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Figure 19-10. Idle Supply Current vs. V 1.2 0.8 0.6 0.4 0.2 Figure 19-11. Idle Supply Current vs. V ATtiny13 128 (Internal RC Oscillator, 4.8 MHz) CC IDLE SUPPLY CURRENT vs. V INTERNAL RC OSCILLATOR, 4 1.5 ...
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Figure 19-12. Idle Supply Current vs. V 19.3 Power-Down Supply Current Figure 19-13. Power-Down Supply Current vs. V 2535J–AVR–08/10 (32 kHz External Clock) CC IDLE SUPPLY CURRENT vs. V 32kHz EXTERNAL CLOCK ...
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Figure 19-14. Power-Down Supply Current vs. V 19.4 Pin Pull-up Figure 19-15. I/O Pin Pull-up Resistor Current vs. Input Voltage (V 160 140 85 ˚C 120 100 ATtiny13 130 POWER-DOWN SUPPLY CURRENT vs. V WATCHDOG TIMER ...
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Figure 19-16. I/O Pin Pull-up Resistor Current vs. Input Voltage (V 85 ºC Figure 19-17. Reset Pull-up Resistor Current vs. Reset Pin Voltage (V 2535J–AVR–08/10 I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE ˚ ...
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Figure 19-18. Reset Pull-up Resistor Current vs. Reset Pin Voltage (V 19.5 Pin Driver Strength Figure 19-19. I/O Pin Source Current vs. Output Voltage (Low Power Ports, V ATtiny13 132 RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE 60 25 ...
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Figure 19-20. I/O Pin Source Current vs. Output Voltage (Low Power Ports, V Figure 19-21. I/O Pin Source Current vs. Output Voltage (Low Power Ports, V 2535J–AVR–08/10 I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE LOW POWER PORTS -40 ...
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Figure 19-22. I/O Pin Sink Current vs. Output Voltage (Low Power Ports, V Figure 19-23. I/O Pin Sink Current vs. Output Voltage (Low Power Ports ATtiny13 134 I/O PIN SINK CURRENT vs. OUTPUT ...
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Figure 19-24. I/O Pin Sink Current vs. Output Voltage (Low Power Ports, V Figure 19-25. I/O Pin Source Current vs. Output Voltage (V 2535J–AVR–08/10 I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE LOW POWER PORTS, 1. ...
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Figure 19-26. I/O Pin Source Current vs. Output Voltage (V Figure 19-27. I/O Pin Source Current vs. Output Voltage (V ATtiny13 136 I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE 35 30 -40 ˚C 25 ˚ ˚ ...
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Figure 19-28. I/O Pin Sink Current vs. Output Voltage (V Figure 19-29. I/O Pin Sink Current vs. Output Voltage (V 2535J–AVR–08/10 I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE 100 ...
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Figure 19-30. I/O Pin Sink Current vs. Output Voltage (V Figure 19-31. Reset Pin as I/O - Source Current vs. Output Voltage (V ATtiny13 138 I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE ...
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Figure 19-32. Reset Pin as I/O - Source Current vs. Output Voltage (V Figure 19-33. Reset Pin as I/O - Source Current vs. Output Voltage (V 2535J–AVR–08/10 RESET PIN AS I/O - SOURCE CURRENT vs. OUTPUT VOLTAGE 2.5 -40 ˚C ...
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Figure 19-34. Reset Pin as I/O - Sink Current vs. Output Voltage (V Figure 19-35. Reset Pin as I/O - Sink Current vs. Output Voltage (V ATtiny13 140 RESET PIN AS I/O - SINK CURRENT vs. OUTPUT VOLTAGE 14 12 ...
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Figure 19-36. Reset Pin as I/O - Sink Current vs. Output Voltage (V 19.6 Pin Thresholds and Hysteresis Figure 19-37. I/O Pin Input Threshold Voltage vs. V 2535J–AVR–08/10 RESET PIN AS I/O - SINK CURRENT vs. OUTPUT VOLTAGE 1.6 1.4 ...
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Figure 19-38. I/O Pin Input Threshold Voltage vs. V Figure 19-39. I/O Pin Input Hysteresis vs. V ATtiny13 142 I/O PIN INPUT THRESHOLD VOLTAGE vs. V VIL, IO PIN READ AS '0' 3 2.5 2 1.5 1 0.5 0 1.5 ...
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Figure 19-40. Reset Pin as I/O - Input Threshold Voltage vs. V Figure 19-41. Reset Pin as I/O - Input Threshold Voltage vs. V 2535J–AVR–08/10 RESET PIN AS I/O - THRESHOLD VOLTAGE vs. V VIH, IO PIN READ AS '1' ...
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Figure 19-42. Reset Pin as I/O - Pin Hysteresis vs. V Figure 19-43. Reset Input Threshold Voltage vs. V ATtiny13 144 RESET PIN PIN HYSTERESIS vs. V 0.7 0.6 -40 ºC 0.5 25 ºC 0.4 85 ºC ...
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Figure 19-44. Reset Input Threshold Voltage vs. V Figure 19-45. Reset Input Pin Hysteresis vs. V 2535J–AVR–08/10 RESET INPUT THRESHOLD VOLTAGE vs. V VIL, IO PIN READ AS '0' 2 ˚C 25 ˚C 0.5 -40 ˚C ...
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BOD Thresholds and Analog Comparator Offset Figure 19-46. BOD Thresholds vs. Temperature (BODLEVEL is 4.3V) Figure 19-47. BOD Thresholds vs. Temperature (BODLEVEL is 2.7V) ATtiny13 146 BOD THRESHOLDS vs. TEMPERATURE BODLEVEL IS 4.3 4.5 4.4 4.3 4.2 -60 -40 ...
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Figure 19-48. BOD Thresholds vs. Temperature (BODLEVEL is 1.8V) Figure 19-49. Bandgap Voltage vs. V 2535J–AVR–08/10 BOD THRESHOLDS vs. TEMPERATURE BODLEVEL IS 1.8 1.9 1.85 1.8 1.75 -60 -40 -20 0 Temperature (C) CC BANDGAP VOLTAGE vs. V 1.06 1.04 ...
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Internal Oscillator Speed Figure 19-50. Calibrated 9.6 MHz RC Oscillator Frequency vs. Temperature Figure 19-51. Calibrated 9.6 MHz RC Oscillator Frequency vs. V ATtiny13 148 CALIBRATED 9.6 MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE 10.3 10.1 9.9 9.7 9.5 5.5 ...
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Figure 19-52. Calibrated 9.6 MHz RC Oscillator Frequency vs. Osccal Value Figure 19-53. Calibrated 4.8 MHz RC Oscillator Frequency vs. Temperature 2535J–AVR–08/10 CALIBRATED 9.6MHz RC OSCILLATOR FREQUENCY vs. OSCCAL VALUE ...
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Figure 19-54. Calibrated 4.8 MHz RC Oscillator Frequency vs. V Figure 19-55. Calibrated 4.8 MHz RC Oscillator Frequency vs. Osccal Value ATtiny13 150 CALIBRATED 4.8 MHz RC OSCILLATOR FREQUENCY vs. V 5.2 5 4.8 4.6 4.4 1.5 2 2.5 3 ...
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Figure 19-56. 128 kHz Watchdog Oscillator Frequency vs. V Figure 19-57. 128 kHz Watchdog Oscillator Frequency vs. Temperature 2535J–AVR–08/10 128 kHz WATCHDOG OSCILLATOR FREQUENCY vs. V 120 115 110 105 100 1.5 2 2.5 3 128 kHz WATCHDOG OSCILLATOR FREQUENCY ...
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Current Consumption of Peripheral Units Figure 19-58. Brownout Detector Current vs. V Figure 19-59. ADC Current vs. V ATtiny13 152 BROWNOUT DETECTOR CURRENT vs 1 ADC ...
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Figure 19-60. Analog Comparator Current vs. V Figure 19-61. Programming Current vs. V 2535J–AVR–08/10 ANALOG COMPARATOR CURRENT vs. V 140 120 100 1 PROGRAMMING CURRENT vs. Vcc 4 3.5 3 2.5 ...
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Current Consumption in Reset and Reset Pulse width Figure 19-62. Reset Supply Current vs. V Figure 19-63. Reset Supply Current vs. V ATtiny13 154 CC Reset Pull-up) RESET SUPPLY CURRENT vs. V 0.1 - 1.0 MHz, EXCLUDING CURRENT THROUGH ...
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Figure 19-64. Reset Pulse Width vs. V 2535J–AVR–08/10 CC RESET PULSE WIDTH vs. V 2500 2000 1500 1000 500 0 1.8 2.1 2.5 2 3.3 3.5 4 4.5 5 5 ºC 25 ºC -40 ...
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Register Summary Address Name Bit 7 0x3F SREG I 0x3E Reserved – 0x3D SPL 0x3C Reserved 0x3B GIMSK – 0x3A GIFR – 0x39 TIMSK0 – 0x38 TIFR0 – 0x37 SPMCSR – 0x36 OCR0A 0x35 MCUCR – 0x34 MCUSR – ...
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Notes: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. 2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI ...
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Instruction Set Summary Mnemonics Operands ARITHMETIC AND LOGIC INSTRUCTIONS ADD Rd, Rr ADC Rd, Rr ADIW Rdl,K SUB Rd, Rr SUBI Rd, K SBC Rd, Rr SBCI Rd, K SBIW Rdl,K AND Rd, Rr ANDI Rd Rd, ...
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Mnemonics Operands ROR Rd ASR Rd SWAP Rd BSET s BCLR s BST Rr, b BLD Rd, b SEC CLC SEN CLN SEZ CLZ SEI CLI SES CLS SEV CLV SET CLT SEH CLH DATA TRANSFER INSTRUCTIONS MOV Rd, Rr ...
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... Body, Lead Pitch 0.50 mm, Micro Lead Frame Package (MLF) 10M1 10-pad Body, Lead Pitch 0.50 mm, Micro Lead Frame Package (MLF) ATtiny13 160 (4) Ordering Code Package ATtiny13V-10PU 8P3 ATtiny13V-10SU 8S2 ATtiny13V-10SUR 8S2 ATtiny13V-10SSU S8S1 ATtiny13V-10SSUR S8S1 ATtiny13V-10MU 20M1 ATtiny13V-10MUR 20M1 ATtiny13V-10MMU 10M1 ...
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Packaging Information 23.1 8P3 Top View PLCS Side View Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA for additional information. 2. Dimensions A and L are measured ...
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... Notes: 1. This drawing is for general information only; refer to EIAJ Drawing EDR-7320 for additional information. 2. Mismatch of the upper and lower dies and resin burrs aren't included. 3. Determines the true geometric position. 4. Values b,C apply to plated terminal. The standard thickness of the plating layer shall measure between 0.007 to .021 mm. Package Drawing Contact: packagedrawings@atmel.com ATtiny13 162 ...
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S8S1 3 Top View e D Side View End View Note: This drawing is for general information only. Refer to JEDEC Drawing MS-012 for proper dimensions, tolerances, datums, etc. 2325 Orchard Parkway San Jose, CA 95131 ...
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D 1 Pin TOP VIEW D2 Pin #1 Notch (0. BOTTOM VIEW Reference JEDEC Standard MO-220, Fig. 1 (SAW Singulation) WGGD-5. Note: 2325 Orchard Parkway San Jose, CA 95131 R ATtiny13 164 ...
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Pin TOP VIEW E1 L BOTTOM VIEW Notes: 1. This package conforms to JEDEC reference MO-229C, Variation VEED-5. 2. The terminal # Lasser-marked Feature. 2325 Orchard Parkway San Jose, CA 95131 R ...
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Errata The revision letter in this section refers to the revision of the ATtiny13 device. 24.1 ATtiny13 Rev. D • EEPROM can not be written below 1.9 Volt 1. EEPROM can not be written below 1.9 Volt Writing the ...
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MHz internal oscillator (CKSEL[1..0] = 01), shortest start-up time Problem fix/ Workaround Avoid the above fuse combinations. Selecting longer start-up time will eliminate the problem. 24.3.4 debugWIRE communication not blocked by lock-bits When debugWIRE on-chip debug is enabled ...
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Datasheet Revision History Please note that the referring page numbers in this section refer to the complete document. 25.1 Rev. 2535J-08/10 Added tape and reel part numbers in recommended for new design” from cover page. Updated last page. 25.2 ...
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... Information” on page Updated “Packaging Information” on page Revision not published. Bits EEMWE/EEWE changed to EEMPE/EEPE in document. Updated “Pinout ATtiny13/ATtiny13V” on page Updated “Write Fuse Low Bits” in Added “Pin Change Interrupt Timing” on page Updated “GIMSK – General Interrupt Mask Register” on page Updated “ ...
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Rev. 2535D-04/ 25.8 Rev. 2535C-02/ 10. 11. 25.9 Rev. 2535B-01/ 10. 11. ...
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Table of Contents Features ..................................................................................................... 1 1 Pin Configurations ................................................................................... 2 2 Overview ................................................................................................... 4 3 General Information ................................................................................. 6 4 CPU Core .................................................................................................. 7 5 Memories ................................................................................................ 15 6 System Clock and Clock Options ......................................................... 23 7 Power Management ...
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System Control and Reset .................................................................... 34 9 Interrupts ................................................................................................ 44 10 I/O Ports .................................................................................................. 48 11 8-bit Timer/Counter0 with PWM ............................................................ 58 12 Timer/Counter Prescaler ....................................................................... 76 13 Analog Comparator ............................................................................... 78 14 Analog to Digital Converter .................................................................. 81 ...
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On-chip Debug System .................................................... 95 16 Self-Programming the Flash ................................................................. 97 17 Memory Programming ......................................................................... 102 2535J–AVR–08/10 14.1 Features ..........................................................................................................81 14.2 Overview ..........................................................................................................81 14.3 Operation .........................................................................................................82 14.4 Starting a Conversion ......................................................................................82 14.5 Prescaling and Conversion Timing ..................................................................83 14.6 ...
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Electrical Characteristics .................................................................... 115 19 Typical Characteristics ........................................................................ 123 20 Register Summary ............................................................................... 156 21 Instruction Set Summary .................................................................... 158 22 Ordering Information ........................................................................... 160 23 Packaging Information ........................................................................ 161 24 Errata ..................................................................................................... 166 ATtiny13 iv 17.6 Serial Programming ...
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Datasheet Revision History ................................................................ 168 Table of Contents....................................................................................... i 2535J–AVR–08/10 24.1 ATtiny13 Rev. D ............................................................................................166 24.2 ATtiny13 Rev. C ............................................................................................166 24.3 ATtiny13 Rev. B .............................................................................................166 24.4 ATtiny13 Rev. A .............................................................................................167 25.1 Rev. 2535J-08/10 ..........................................................................................168 25.2 Rev. 2535I-05/08 ...........................................................................................168 25.3 ...
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... Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI- TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT ...