ATTINY13V-10MMU Atmel, ATTINY13V-10MMU Datasheet

MCU AVR 1K ISP FLASH 1.8V 10-QFN

ATTINY13V-10MMU

Manufacturer Part Number
ATTINY13V-10MMU
Description
MCU AVR 1K ISP FLASH 1.8V 10-QFN
Manufacturer
Atmel
Series
AVR® ATtinyr
Datasheets

Specifications of ATTINY13V-10MMU

Core Processor
AVR
Core Size
8-Bit
Speed
10MHz
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
6
Program Memory Size
1KB (512 x 16)
Program Memory Type
FLASH
Eeprom Size
64 x 8
Ram Size
64 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
10-MLF®, 10-DFN
Processor Series
ATTINY1x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
64 B
Interface Type
SPI
Maximum Clock Frequency
10 MHz
Number Of Programmable I/os
6
Number Of Timers
1
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 4 Channel
Package
10MLF EP
Device Core
AVR
Family Name
ATtiny
Maximum Speed
10 MHz
Operating Supply Voltage
2.5|3.3|5 V
For Use With
ATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEM
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Connectivity
-
Lead Free Status / Rohs Status
 Details
Features
High Performance, Low Power AVR
Advanced RISC Architecture
High Endurance Non-volatile Memory segments
Peripheral Features
Special Microcontroller Features
I/O and Packages
Operating Voltage:
Speed Grade
Industrial Temperature Range
Low Power Consumption
– 120 Powerful Instructions – Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
– Up to 20 MIPS Througput at 20 MHz
– 1K Bytes of In-System Self-programmable Flash program memory
– 64 Bytes EEPROM
– 64 Bytes Internal SRAM
– Write/Erase cyles: 10,000 Flash/100,000 EEPROM
– Data retention: 20 years at 85°C/100 years at 25°C (see
– Programming Lock for Self-Programming Flash & EEPROM Data Security
– One 8-bit Timer/Counter with Prescaler and Two PWM Channels
– 4-channel, 10-bit ADC with Internal Voltage Reference
– Programmable Watchdog Timer with Separate On-chip Oscillator
– On-chip Analog Comparator
– debugWIRE On-chip Debug System
– In-System Programmable via SPI Port
– External and Internal Interrupt Sources
– Low Power Idle, ADC Noise Reduction, and Power-down Modes
– Enhanced Power-on Reset Circuit
– Programmable Brown-out Detection Circuit
– Internal Calibrated Oscillator
– 8-pin PDIP/SOIC: Six Programmable I/O Lines
– 20-pad MLF: Six Programmable I/O Lines
– 1.8 - 5.5V for ATtiny13V
– 2.7 - 5.5V for ATtiny13
– ATtiny13V: 0 - 4 MHz @ 1.8 - 5.5V, 0 - 10 MHz @ 2.7 - 5.5V
– ATtiny13: 0 - 10 MHz @ 2.7 - 5.5V, 0 - 20 MHz @ 4.5 - 5.5V
– Active Mode:
– Power-down Mode:
• 1 MHz, 1.8V: 240 µA
• < 0.1 µA at 1.8V
®
8-Bit Microcontroller
page
6)
8-bit
Microcontroller
with 1K Bytes
In-System
Programmable
Flash
ATtiny13
ATtiny13V
Summary
Rev. 2535JS–AVR–08/10

Related parts for ATTINY13V-10MMU

ATTINY13V-10MMU Summary of contents

Page 1

... Operating Voltage: – 1.8 - 5.5V for ATtiny13V – 2.7 - 5.5V for ATtiny13 • Speed Grade – ATtiny13V MHz @ 1.8 - 5.5V MHz @ 2.7 - 5.5V – ATtiny13 MHz @ 2.7 - 5.5V MHz @ 4.5 - 5.5V • Industrial Temperature Range • Low Power Consumption – Active Mode: • ...

Page 2

... Pin Configurations Figure 1-1. Pinout ATtiny13/ATtiny13V (PCINT5/RESET/ADC0/dW) PB5 (PCINT3/CLKI/ADC3) PB3 (PCINT4/ADC2) PB4 (PCINT5/RESET/ADC0/dW) PB5 (PCINT3/CLKI/ADC3) PB3 (PCINT4/ADC2) PB4 NOTE: Bottom pad should be soldered to ground. DNC: Do Not Connect (PCINT5/RESET/ADC0/dW) PB5 (PCINT3/CLKI/ADC3) PB3 (PCINT4/ADC2) PB4 NOTE: Bottom pad should be soldered to ground. DNC: Do Not Connect ...

Page 3

Pin Descriptions 1.1.1 VCC Digital supply voltage. 1.1.2 GND Ground. 1.1.3 Port B (PB5:PB0) Port 6-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics ...

Page 4

Overview The ATtiny13 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny13 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to ...

Page 5

... Hardware Reset. The ADC Noise Reduction mode stops the CPU and all I/O modules except ADC, to minimize switching noise during ADC conversions. The device is manufactured using Atmel’s high density non-volatile memory technology. The On-chip ISP Flash allows the Program memory to be re-programmed In-System through an SPI serial interface conventional non-volatile memory programmer On-chip boot code running on the AVR core ...

Page 6

... General Information 3.1 Resources A comprehensive set of drivers, application notes, data sheets and descriptions on development tools are available for download at http://www.atmel.com/avr. 3.2 Code Examples This documentation contains simple code examples that briefly show how to use various parts of the device. These code examples assume that the part specific header file is included before compilation ...

Page 7

Register Summary Address Name Bit 7 0x3F SREG I 0x3E Reserved – 0x3D SPL 0x3C Reserved 0x3B GIMSK – 0x3A GIFR – 0x39 TIMSK0 – 0x38 TIFR0 – 0x37 SPMCSR – 0x36 OCR0A 0x35 MCUCR – 0x34 MCUSR – ...

Page 8

Notes: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. 2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI ...

Page 9

Instruction Set Summary Mnemonics Operands ARITHMETIC AND LOGIC INSTRUCTIONS ADD Rd, Rr ADC Rd, Rr ADIW Rdl,K SUB Rd, Rr SUBI Rd, K SBC Rd, Rr SBCI Rd, K SBIW Rdl,K AND Rd, Rr ANDI Rd Rd, ...

Page 10

Mnemonics Operands ROR Rd ASR Rd SWAP Rd BSET s BCLR s BST Rr, b BLD Rd, b SEC CLC SEN CLN SEZ CLZ SEI CLI SES CLS SEV CLV SET CLT SEH CLH DATA TRANSFER INSTRUCTIONS MOV Rd, Rr ...

Page 11

... Body, Lead Pitch 0.50 mm, Micro Lead Frame Package (MLF) 2535JS–AVR–08/10 (4) Ordering Code Package ATtiny13V-10PU ATtiny13V-10SU ATtiny13V-10SUR ATtiny13V-10SSU S8S1 ATtiny13V-10SSUR S8S1 ATtiny13V-10MU 20M1 ATtiny13V-10MUR 20M1 ATtiny13V-10MMU 10M1 ATtiny13V-10MMUR 10M1 ATtiny13-20PU ATtiny13-20SU ATtiny13-20SUR ATtiny13-20SSU S8S1 ATtiny13-20SSUR S8S1 ATtiny13-20MU 20M1 ATtiny13-20MUR 20M1 ATtiny13-20MMU 10M1 ATtiny13-20MMUR 10M1 117. ...

Page 12

Packaging Information 7.1 8P3 Top View PLCS Side View Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA for additional information. 2. Dimensions A and L are measured ...

Page 13

... Notes: 1. This drawing is for general information only; refer to EIAJ Drawing EDR-7320 for additional information. 2. Mismatch of the upper and lower dies and resin burrs aren't included. 3. Determines the true geometric position. 4. Values b,C apply to plated terminal. The standard thickness of the plating layer shall measure between 0.007 to .021 mm. Package Drawing Contact: packagedrawings@atmel.com 2535JS–AVR–08/ ...

Page 14

S8S1 3 Top View e D Side View End View Note: This drawing is for general information only. Refer to JEDEC Drawing MS-012 for proper dimensions, tolerances, datums, etc. 2325 Orchard Parkway San Jose, CA 95131 ...

Page 15

D 1 Pin TOP VIEW D2 Pin #1 Notch (0. BOTTOM VIEW Reference JEDEC Standard MO-220, Fig. 1 (SAW Singulation) WGGD-5. Note: 2325 Orchard Parkway San Jose, CA 95131 R 2535JS–AVR–08/10 E ...

Page 16

Pin TOP VIEW E1 L BOTTOM VIEW Notes: 1. This package conforms to JEDEC reference MO-229C, Variation VEED-5. 2. The terminal # Lasser-marked Feature. 2325 Orchard Parkway San Jose, CA 95131 R ...

Page 17

Errata The revision letter in this section refers to the revision of the ATtiny13 device. 8.1 ATtiny13 Rev. D • EEPROM can not be written below 1.9 Volt 1. EEPROM can not be written below 1.9 Volt Writing the ...

Page 18

MHz internal oscillator (CKSEL[1..0] = 01), shortest start-up time Problem fix/ Workaround Avoid the above fuse combinations. Selecting longer start-up time will eliminate the problem. 8.3.4 debugWIRE communication not blocked by lock-bits When debugWIRE on-chip debug is enabled ...

Page 19

Datasheet Revision History Please note that the referring page numbers in this section refer to the complete document. 9.1 Rev. 2535J-08/10 Added tape and reel part numbers in recommended for new design” from cover page. Updated last page. 9.2 ...

Page 20

... Information” on page Updated “Packaging Information” on page Revision not published. Bits EEMWE/EEWE changed to EEMPE/EEPE in document. Updated “Pinout ATtiny13/ATtiny13V” on page Updated “Write Fuse Low Bits” in Table 17-13 on page Added “Pin Change Interrupt Timing” on page Updated “GIMSK – General Interrupt Mask Register” on page Updated “ ...

Page 21

Rev. 2535D-04/ 9.8 Rev. 2535C-02/ 10. 11. 9.9 Rev. 2535B-01/ 10. 11. ...

Page 22

... Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI- TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT ...

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