MC9S12C32MFUE25 Freescale Semiconductor, MC9S12C32MFUE25 Datasheet - Page 231

• Manufacturer Part Number: MC9S12C32MFUE25
• Description: IC MCU 32K FLASH 25MHZ 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12C32MFUE25

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 80-QFP
• Processor Series: S12C
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 2 KB
• Interface Type: CAN/SCI/SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 60
• Number Of Timers: 8
• Operating Supply Voltage: 3.3 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: M68EVB912C32EE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• For Use With: CML12C32SLK - KIT STUDENT LEARNING 16BIT HCS12
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

8.3.2.3
This register controls power down, interrupt, and external trigger. Writes to this register will abort current
conversion sequence but will not start a new sequence.
Read: Anytime
Write: Anytime
Freescale Semiconductor
Module Base + 0x0002
ETRIGLE
ETRIGP
ETRIGE
Reset
ADPU
AFFC
Field
AWAI
7
6
5
4
3
2
W
R
ADPU
ATD Power Down — This bit provides on/off control over the ATD10B8C block allowing reduced MCU power
consumption. Because analog electronic is turned off when powered down, the ATD requires a recovery time
period after ADPU bit is enabled.
0 Power down ATD
1 Normal ATD functionality
ATD Fast Flag Clear All
0 ATD flag clearing operates normally (read the status register ATDSTAT1 before reading the result register to
1 Changes all ATD conversion complete flags to a fast clear sequence. Any access to a result register will cause
ATD Power Down in Wait Mode — When entering Wait Mode this bit provides on/off control over the ATD10B8C
block allowing reduced MCU power. Because analog electronic is turned off when powered down, the ATD
requires a recovery time period after exit from Wait mode.
0 ATD continues to run in Wait mode
1 Halt conversion and power down ATD during Wait mode
External Trigger Level/Edge Control — This bit controls the sensitivity of the external trigger signal. See
Table 8-2
External Trigger Polarity — This bit controls the polarity of the external trigger signal. See
External Trigger Mode Enable — This bit enables the external trigger on ATD channel 7. The external trigger
allows to synchronize sample and ATD conversions processes with external events.
0 Disable external trigger
1 Enable external trigger
Note: The conversion results for the external trigger ATD channel 7 have no meaning while external trigger mode
ATD Control Register 2 (ATDCTL2)
0
7
clear the associate CCF flag).
the associate CCF flag to clear automatically.
After exiting Wait mode with an interrupt conversion will resume. But due to the recovery time the result of this
conversion should be ignored.
is enabled.
for details.
= Unimplemented or Reserved
AFFC
0
6
Figure 8-5. ATD Control Register 2 (ATDCTL2)
Table 8-1. ATDCTL2 Field Descriptions
AWAI
MC9S12C-Family / MC9S12GC-Family
0
5
ETRIGLE
Rev 01.24
0
4
Chapter 8 Analog-to-Digital Converter (ATD10B8C) Block Description
Description
ETRIGP
0
3
ETRIGE
0
2
ASCIE
0
1
Table 8-2
for details.
ASCIF
0
0
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