PIC14000-04/SS Microchip Technology, PIC14000-04/SS Datasheet - Page 20

• Manufacturer Part Number: PIC14000-04/SS
• Description: IC MCU OTP 4KX14 A/D 28SSOP
• Manufacturer: Microchip Technology
• Series: PIC® 14r

Specifications of PIC14000-04/SS

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: I²C
• Peripherals: POR, Temp Sensor, WDT
• Number Of I /o: 20
• Program Memory Size: 7KB (4K x 14)
• Program Memory Type: OTP
• Ram Size: 192 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 6 V
• Data Converters: Slope A/D
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 28-SSOP
• Processor Series: PIC14000
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 192 B
• Interface Type: SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 22
• Number Of Timers: 1
• Operating Supply Voltage: 2.7 V to 6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ICE2000
• Minimum Operating Temperature: 0 C
• On-chip Adc: 14 bit
• For Use With: 309-1025 - ADAPTER 28-SSOP TO 28-DIPXLT28SS-1 - SOCKET TRANSITION ICE 28SSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC14000
4.2.2.4
This register contains the individual enable bits for the
Peripheral interrupts including A/D capture event, I
serial port, PORTC change and A/D capture timer
overflow, and external push button.
FIGURE 4-6:
DS40122B-page 20
bit7
CMIE
R/W
PIE1 REGISTER
R
—
PIE1 REGISTER
—
R
PBIE I
R/W
2
CIE
R/W
RCIE
R/W
ADCIE
R/W
Preliminary
2
C
OVFIE
R/W
bit0
OVFIE: A/D Counter Overflow Interrupt Enable
1 = Enables A/D counter overflow interrupt
0 = Disables A/D counter overflow interrupt
ADCIE: A/D Capture Interrupt Enable
1 = A/D capture interrupt is enabled
0 = A/D capture interrupt is disabled
RCIE:
1 = Enables RCIF interrupt on pins, RC<7:4>
0 = Disables RCIF interrupt
I
1 = Enables I
0 = Disables I
PBIE: External Pushbutton Interrupt Enable
1 = Enable PBTN (pushbutton) interrupt on OSC1/PBTN.
0 = Disable PBTN interrupt on OSC1/PBTN
Unimplemented. Read as ‘0’
Unimplemented. Read as ‘0’
CMIE: Programmable Reference Comparator Interrupt Enable
1 = Enable programmable reference comparator trip
0 = Disable programmable reference comparator trip
2
CIE: I
Note:
(Note this interrupt not available in HS mode).
Register:
Address:
POR value:
2
PORTC Interrupt on change Enable
C Port Interrupt Enable
INTCON<6> must be enabled to enable
any interrupt in PIE1.
2
2
CIF interrupt
CIF interrupt
PIE1
8Ch
00h
W:
R:
U:
1996 Microchip Technology Inc.
Writable
Readable
Unimplemented,
read as '0'