PIC12F675-E/SN Microchip Technology, PIC12F675-E/SN Datasheet - Page 5

• Manufacturer Part Number: PIC12F675-E/SN
• Description: IC MCU CMOS 1K FLASH W/AD 8-SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 12Fr

Specifications of PIC12F675-E/SN

• Program Memory Type: FLASH
• Program Memory Size: 1.75KB (1K x 14)
• Package / Case: 8-SOIC (3.9mm Width)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Peripherals: POR, WDT
• Number Of I /o: 5
• Eeprom Size: 128 x 8
• Ram Size: 64 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Processor Series: PIC12F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 64 B
• Interface Type: RS- 232/USB
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 6
• Number Of Timers: 2
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 53270-913
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163014, DM164120-4
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 4-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Connectivity: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

2.3
The Program/Verify mode is entered by holding pins clock
and data low while raising MCLR pin from V
(high voltage). Apply V
the user program memory, data memory and the configu-
ration memory can be accessed and programmed in
serial fashion. Clock is Schmitt Trigger and data is TTL
input in this mode. GP4 (PIC12F629/675) or RA4
(PIC16F630/676) is tri-state, regardless of use setting.
The sequence that enters the device into the Program-
ming/Verify mode places all other logic into the Reset
state (the MCLR pin was initially at V
that all I/O’s are in the Reset state (high-impedance
inputs).
FIGURE 2-2:
The normal sequence for programming is to use the
Load Data command to set a value to be written at the
selected address. Issue the Begin Programming
command followed by a Read Data command to verify
and then increment the address.
TABLE 2-1:
© 2005 Microchip Technology Inc.
Load Configuration
Load Data for Program Memory
Load Data for Data Memory
Read Data from Program Memory
Read Data from Data Memory
Increment Address
Begin Programming
Begin Programming
End Programming
Bulk Erase Program Memory
Bulk Erase Data Memory
CLOCK
DATA
V
V
DD
PP
Program/Verify Mode
Command
COMMAND MAPPING FOR PIC12F629/675/PIC16F630/676
T
SDATA = Input
PPDP
DD
ENTERING HIGH
VOLTAGE PROGRAM/
VERIFY MODE
and data. Once in this mode,
T
HLD
0
IL
PIC12F629/675/PIC16F630/676
). This means
IL
to V
X
X
X
X
X
X
0
0
0
X
X
IHH
Mapping (MSb … LSb)
X
X
X
X
X
X
0
1
0
X
X
A device Reset will clear the PC and set the address to
‘0’. The Increment Address command will increment
the PC. The Load Configuration command will set the
PC to 0x2000. The available commands are shown in
Table 2-1.
2.3.1
The clock pin is used as a clock input pin and the data
pin is used for entering command bits and data input/out-
put during serial operation. To input a command, the
clock pin (CLOCK) is cycled six times. Each command
bit is latched on the falling edge of the clock with the LSb
of the command being input first. The data on pin DATA
is required to have a minimum setup and hold time (see
Table 5-1), with respect to the falling edge of the clock.
Commands that have data associated with them (Read
and Load) are specified to have a minimum delay of 1 μs
between the command and the data. After this delay, the
clock pin is cycled 16 times with the first cycle being a
Start bit and the last cycle being a Stop bit. Data is also
input and output LSb first.
Therefore, during a read operation, the LSb will be
transmitted onto pin DATA on the rising edge of the
second cycle. During a load operation, the LSb will be
latched on the falling edge of the second cycle. A
minimum 1 μs delay is also specified between
consecutive commands.
All commands are transmitted LSb first. Data words are
also transmitted LSb first. The data is transmitted on
the rising edge and latched on the falling edge of the
clock. To allow for decoding of commands and reversal
of data pin configuration, a time separation of at least
1 μs is required between a command and a data word
(or another command).
The commands that are available are described in
Table 2-1.
0
0
0
0
0
0
1
1
1
1
1
0
0
0
1
1
1
0
0
0
0
0
SERIAL PROGRAM/VERIFY
OPERATION
0
1
1
0
0
1
0
0
1
0
1
0
0
1
0
1
0
0
0
0
1
1
0, data (14), 0
0, data (14), 0
0, data (8), zero (6), 0
0, data (14), 0
0, data (8), zero (6), 0
Internally Timed
Externally Timed
Internally Timed
Internally Timed
DS41191D-page 5
Data