MC9S12E64CFUE Freescale Semiconductor, MC9S12E64CFUE Datasheet - Page 503
MC9S12E64CFUE
Manufacturer Part Number
MC9S12E64CFUE
Description
IC MCU 64K FLASH 25MHZ 80-QFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Specifications of MC9S12E64CFUE
Core Processor
HCS12
Core Size
16-Bit
Speed
25MHz
Connectivity
EBI/EMI, I²C, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
60
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 2.75 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
80-QFP
Package
80PQFP
Family Name
HCS12
Maximum Speed
25 MHz
Operating Supply Voltage
2.5|3.3|5 V
Data Bus Width
16 Bit
Number Of Programmable I/os
60
Interface Type
SCI/SPI
On-chip Adc
16-chx10-bit
On-chip Dac
2-chx8-bit
Number Of Timers
12
Processor Series
S12E
Core
HCS12
Data Ram Size
4 KB
Maximum Clock Frequency
25 MHz
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Minimum Operating Temperature
- 40 C
Controller Family/series
HCS12/S12X
No. Of I/o's
58
Ram Memory Size
4KB
Cpu Speed
25MHz
No. Of Timers
4
Embedded Interface Type
I2C, SCI, SPI
Rohs Compliant
Yes
For Use With
M68EVB912E128 - BOARD EVAL FOR MC9S12E128/64
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
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Manufacturer
Quantity
Price
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Manufacturer:
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Quantity:
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Manufacturer:
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16.4.3.2
A breakpoint request to the CPU can be created if BKCEN in DBGC2 is set. Breakpoints based on a
successful comparator C match can be accomplished regardless of the mode of operation for comparator
A or B, and do not affect the status of the ARM bit. TAGC in DBGC2 is used to select either tagged or
forced breakpoint requests for comparator C. Breakpoints based on comparator C are disabled in LOOP1
mode.
16.5
The DBG module is disabled after reset.
The DBG module cannot cause a MCU reset.
16.6
The DBG contains one interrupt source. If a breakpoint is requested and BDM in DBGC2 is cleared, an
SWI interrupt will be generated.
Freescale Semiconductor
BEGIN
Resets
Interrupts
0
0
0
0
1
1
1
1
Breakpoint Based on Comparator C
Because breakpoints cannot be disabled when the DBG is armed, one must
be careful to avoid an “infinite breakpoint loop” when using tagged-type C
breakpoints while the DBG is armed. If BDM breakpoints are selected,
executing a TRACE1 instruction before the GO instruction is the
recommended way to avoid re-triggering a breakpoint if one does not wish
to de-arm the DBG. If SWI breakpoints are selected, disarming the DBG in
the SWI interrupt service routine is the recommended way to avoid
re-triggering a breakpoint.
TRGSEL
0
0
1
1
0
0
1
1
DBGBRK
MC9S12E128 Data Sheet, Rev. 1.07
Table 16-26. Breakpoint Setup
0
1
0
1
0
1
0
1
Fill trace buffer until trigger address
(no CPU breakpoint — keep running)
Fill trace buffer until trigger address, then a forced breakpoint
request occurs
Fill trace buffer until trigger opcode is about to execute
(no CPU breakpoint — keep running)
Fill trace buffer until trigger opcode about to execute, then a
tagged breakpoint request occurs
Start trace buffer at trigger address
(no CPU breakpoint — keep running)
Start trace buffer at trigger address, a forced breakpoint
request occurs when trace buffer is full
Start trace buffer at trigger opcode
(no CPU breakpoint — keep running)
Start trace buffer at trigger opcode, a forced breakpoint request
occurs when trace buffer is full
NOTE
Type of Debug Run
Chapter 16 Debug Module (DBGV1)
503
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