C8051F301-GS Silicon Laboratories Inc, C8051F301-GS Datasheet - Page 8

• Manufacturer Part Number: C8051F301-GS
• Description: IC 8051 MCU 8K FLASH 14-SOIC
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F30xr

Specifications of C8051F301-GS

• Program Memory Type: FLASH
• Program Memory Size: 8KB (8K x 8)
• Package / Case: 14-SOIC (3.9mm Width), 14-SOL
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: C8051F3x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: I2C/SMBus/UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 8
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F300DK
• Minimum Operating Temperature: - 40 C
• Package: 14SOIC
• Device Core: 8051
• Family Name: C8051F30x
• Maximum Speed: 25 MHz
• Operating Supply Voltage: 3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 770-1006 - ISP 4PORT FOR SILABS C8051F MCU336-1444 - ADAPTER PROGRAM TOOLSTICK F300336-1319 - REFERENCE DESIGN STEPPER MOTOR
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1536-5

C8051F300/1/2/3/4/5
10. Flash Memory
11. Oscillators
12. Port Input/Output
13. SMBus
14. UART0
15. Timers
16. Programmable Counter Array
17. C2 Interface
8
Figure 10.1. Flash Program Memory Map................................................................ 91
Figure 11.1. Oscillator Diagram................................................................................ 97
Figure 11.2. 32.768 kHz External Crystal Example................................................ 101
Figure 12.1. Port I/O Functional Block Diagram ..................................................... 103
Figure 12.2. Port I/O Cell Block Diagram ............................................................... 103
Figure 12.3. Crossbar Priority Decoder with XBR0 = 0x00 .................................... 104
Figure 12.4. Crossbar Priority Decoder with XBR0 = 0x44 .................................... 105
Figure 13.1. SMBus Block Diagram ....................................................................... 111
Figure 13.2. Typical SMBus Configuration ............................................................. 112
Figure 13.3. SMBus Transaction ............................................................................ 113
Figure 13.4. Typical SMBus SCL Generation......................................................... 117
Figure 13.5. Typical Master Transmitter Sequence................................................ 123
Figure 13.6. Typical Master Receiver Sequence.................................................... 124
Figure 13.7. Typical Slave Receiver Sequence...................................................... 125
Figure 13.8. Typical Slave Transmitter Sequence.................................................. 126
Figure 14.1. UART0 Block Diagram ....................................................................... 131
Figure 14.2. UART0 Baud Rate Logic .................................................................... 132
Figure 14.3. UART Interconnect Diagram .............................................................. 133
Figure 14.4. 8-Bit UART Timing Diagram............................................................... 133
Figure 14.5. 9-Bit UART Timing Diagram............................................................... 134
Figure 14.6. UART Multi-Processor Mode Interconnect Diagram .......................... 135
Figure 15.1. T0 Mode 0 Block Diagram.................................................................. 144
Figure 15.2. T0 Mode 2 Block Diagram.................................................................. 145
Figure 15.3. T0 Mode 3 Block Diagram.................................................................. 146
Figure 15.4. Timer 2 16-Bit Mode Block Diagram .................................................. 151
Figure 15.5. Timer 2 8-Bit Mode Block Diagram .................................................... 152
Figure 16.1. PCA Block Diagram............................................................................ 155
Figure 16.2. PCA Counter/Timer Block Diagram.................................................... 156
Figure 16.3. PCA Interrupt Block Diagram ............................................................. 157
Figure 16.4. PCA Capture Mode Diagram.............................................................. 158
Figure 16.5. PCA Software Timer Mode Diagram .................................................. 159
Figure 16.6. PCA High Speed Output Mode Diagram............................................ 160
Figure 16.7. PCA Frequency Output Mode ............................................................ 161
Figure 16.8. PCA 8-Bit PWM Mode Diagram ......................................................... 162
Figure 16.9. PCA 16-Bit PWM Mode...................................................................... 163
Figure 16.10. PCA Module 2 with Watchdog Timer Enabled ................................. 164
Figure 17.1. Typical C2 Pin Sharing....................................................................... 175
Rev. 2.9