ST7FLITE19F1M6 STMicroelectronics, ST7FLITE19F1M6 Datasheet - Page 71

IC MCU 8BIT 4K 20-SOIC

ST7FLITE19F1M6

Manufacturer Part Number
ST7FLITE19F1M6
Description
IC MCU 8BIT 4K 20-SOIC
Manufacturer
STMicroelectronics
Series
ST7r
Datasheet

Specifications of ST7FLITE19F1M6

Core Processor
ST7
Core Size
8-Bit
Speed
8MHz
Connectivity
SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
15
Program Memory Size
4KB (4K x 8)
Program Memory Type
FLASH
Eeprom Size
128 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 5.5 V
Data Converters
A/D 7x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-SOIC (7.5mm Width)
Processor Series
ST7FLITE1x
Core
ST7
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
15
Number Of Timers
1 x 12 bit / 2 x 8 bit
Operating Supply Voltage
2.4 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
ST7FLIT2-COS/COM, ST7FLITE-SK/RAIS, ST7MDT10-DVP3, ST7MDT10-EMU3, STX-RLINK
Minimum Operating Temperature
- 40 C
On-chip Adc
7 bit x 10 bit
For Use With
497-5858 - EVAL BOARD PLAYBACK ST7FLITE497-5049 - KIT STARTER RAISONANCE ST7FLITE497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
497-2133-5

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SERIAL PERIPHERAL INTERFACE (Cont’d)
11.4.3.1 Functional Description
A basic example of interconnections between a
single master and a single slave is illustrated in
Figure
The MOSI pins are connected together and the
MISO pins are connected together. In this way
data is transferred serially between master and
slave (most significant bit first).
The communication is always initiated by the mas-
ter. When the master device transmits data to a
slave device via MOSI pin, the slave device re-
Figure 42. Single Master/ Single Slave Application
42.
MSBit
8-BIT SHIFT REGISTER
GENERATOR
CLOCK
SPI
MASTER
LSBit
MOSI
SCK
SS
MISO
+5V
sponds by sending data to the master device via
the MISO pin. This implies full duplex communica-
tion with both data out and data in synchronized
with the same clock signal (which is provided by
the master device via the SCK pin).
To use a single data line, the MISO and MOSI pins
must be connected at each node ( in this case only
simplex communication is possible).
Four possible data/clock timing relationships may
be chosen (see
must be programmed with the same timing mode.
MISO
MOSI
SCK
SS
Figure
8-BIT SHIFT REGISTER
MSBit
Not used if SS is managed
by software
45) but master and slave
SLAVE
ST7LITE1
LSBit
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