ATMEGA406-1AAU Atmel, ATMEGA406-1AAU Datasheet
ATMEGA406-1AAU
Specifications of ATMEGA406-1AAU
Available stocks
Related parts for ATMEGA406-1AAU
ATMEGA406-1AAU Summary of contents
Page 1
... LQFP • Operating Voltage: 4.0 - 25V • Maximum Withstand Voltage (High-voltage pins): 28V • Temperature Range: -30°C to 85°C – Speed Grade: 1 MHz ® 8-bit Microcontroller 8-bit Microcontroller with 40K Bytes In-System Programmable Flash ATmega406 Preliminary Summary 2548ES–AVR–07/06 ...
Page 2
... Disclaimer Typical values contained in this datasheet are based on simulations and characterization of other AVR microcontrollers manufactured on the same process technology. Min and Max values will be available after the device is characterized. ATmega406 2 Pinout ATmega406. Top View SGND 1 (ADC0 /PCINT0 ) PA0 2 (ADC1 /PCINT1 ) PA1 ...
Page 3
... Overview The ATmega406 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega406 achieves throughputs approaching 1 MIPS at 1 MHz. 2.1 Block Diagram Figure 2-1. Block Diagram XTAL1 Oscillator Circuits / Clock Generation ...
Page 4
... Cell Balancing FETs, and a voltage regulator on a monolithic chip, the Atmel ATmega406 is a powerful microcontroller that provides a highly flexible and cost effective solution for Li-ion Smart Battery applications. The ATmega406 AVR is supported with a full suite of program and system development tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators, and On-chip Debugger. ...
Page 5
... As inputs, Port A pins that are externally pulled low will source current if the pull-up resistors are activated. The Port A pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port A also serves the functions of various special features of the ATmega406 as listed in nate Functions of Port A” on page 2.2.9 ...
Page 6
... As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port D also serves the functions of various special features of the ATmega406 as listed in nate Functions of Port D” on page 2.2.12 SCL SMBUS clock, Open Drain bidirectional pin ...
Page 7
... XTAL1 Input to the inverting Oscillator amplifier. 2.2.22 XTAL2 Output from the inverting Oscillator amplifier. 3. Resources A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr. 2548ES–AVR–07/06 ATmega406 7 ...
Page 8
... Reserved – (0xC5) Reserved – (0xC4) Reserved – (0xC3) Reserved – (0xC2) Reserved – (0xC1) Reserved – (0xC0) CCSR – ATmega406 8 Bit 6 Bit 5 Bit 4 Bit 3 – – – – – – – – – – – – – – – ...
Page 9
... CTC1 – – – – – – – – – – – VADC3D ATmega406 Bit 2 Bit 1 Bit 0 – – – TWBDT1 TWBDT0 TWBCIP – TWEN – TWIE TWGCE – TWPS1 TWPS0 – – – ...
Page 10
... EEARH – 0x21 (0x41) EEARL 0x20 (0x40) EEDR 0x1F (0x3F) EECR – 0x1E (0x3E) GPIOR0 0x1D (0x3D) EIMSK – 0x1C (0x3C) EIFR – ATmega406 10 Bit 6 Bit 5 Bit 4 Bit 3 – – – – – – – VADMUX3 – – – – ...
Page 11
... When using the I/O specific commands IN and OUT, the I/O addresses $00 - $3F must be used. When addressing I/O regis- ters as data space using LD and ST instructions, $20 must be added to these addresses. The ATmega406 is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions ...
Page 12
... Branch if Half Carry Flag Cleared BRTS k Branch if T Flag Set BRTC k Branch if T Flag Cleared BRVS k Branch if Overflow Flag is Set BRVC k Branch if Overflow Flag is Cleared ATmega406 12 Description Rd ← ← Rdh:Rdl ← Rdh:Rdl + K Rd ← ← ← ← Rdh:Rdl ← Rdh:Rdl - K Rd ← Rd • ← Rd • ← ...
Page 13
... Rr, Y ← ← (Y) ← ← Rr (Z) ← Rr (Z) ← Rr, Z ← ← (Z) ← ← Rr (k) ← ← (Z) Rd ← (Z) Rd ← (Z), Z ← Z+1 (Z) ← R1:R0 Rd ← P ATmega406 Operation Flags #Clocks None None None None Z,C,N,V Z,C,N,V Z,C,N,V Z,C,N,V Z,C,N,V ...
Page 14
... Rd Pop Register from Stack MCU CONTROL INSTRUCTIONS NOP No Operation SLEEP Sleep WDR Watchdog Reset BREAK Break ATmega406 14 Description P ← Rr STACK ← ← STACK (see specific descr. for Sleep function) (see specific descr. for WDR/timer) For On-chip Debug Only Operation Flags #Clocks ...
Page 15
... Pb-free packaging alternative, complies to the European Directive for Restriction of Hazardous Substances (RoHS direc- tive). Also Halide free and fully Green. 48AA 48-lead 1.44 mm body, 0.5 mm lead pitch, Low Profile Plastic Quad Flat Package (LQFP) 2548ES–AVR–07/06 Ordering Code Package (2) ATmega406-1AAU 48AA Package Type ATmega406 (1) Operation Range Industrial (-30°C to 85°C) ...
Page 16
... This package conforms to JEDEC reference MS-026, Variation BBC. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.08 mm maximum. 2325 Orchard Parkway San Jose, CA 95131 R ATmega406 16 B PIN 1 IDENTIFIER ...
Page 17
... Cell 1 and 2. age at Cell 4. The worst-case error is when Cell 1, Cell 2 and Cell 3 are balanced while Cell 4 voltage deviates from the voltage at Cell 1, 2 and 3. 18, shows the error of Cell2, Cell3 and Cell4 with 5% and 10% unbal- ATmega406 17 ...
Page 18
... V-ADC is enabled by the VADEN bit. The spike will be approximately 50mV and lasts for about 5ms, and it will affect any ongoing current accumulation in the CC-ADC, as well as V-ADC conversions in the period of the spike. ATmega406 18 CM Offset with unbalanced cells. Figure 9-2 on page 19 illustrates the Voltage Reference spike. 2548ES– ...
Page 19
... Figure 8-2. VADMUX3:0 Problem workaround: To get correct temperature measurement, the VADSC bit should not be written until the spike has settled (external decoupling capacitor of 1μF). 2548ES–AVR–07/06 Voltage Reference Spike Voltage V~50mV 1.1 V VADEN XXX ATmega406 VREF t ~< 5ms VTEMP time 19 ...
Page 20
... The CM level for Cell 3 will change if Cell 1 and/or Cell 2 voltage deviates from the d. The CM level for Cell 4 will change if Cell 1, Cell 2 and/or Cell 3 deviate from the volt- Figure 9-1 on page anced cells. ATmega406 20 °C offset. voltage at Cell 3. The worst-case error is when Cell 1 and 2 are balanced while Cell 3 voltage deviates from the voltage at Cell 1 and 2 ...
Page 21
... The first 9 results would be inaccurate, but the 10th conversion will be correct. Figure 9-4 on page 22 ature conversions in a row (external decoupling capacitor of 1μF). 2548ES–AVR–07/06 CM Offset with unbalanced cells. illustrates the spike on the Voltage Reference when doing 10 temper- ATmega406 21 ...
Page 22
... The cell conversion will have an Offset-error depending on the Common Mode (CM) level. This means that the error of a cell is depending on the voltage of the lower cells. The CM Offset is calibrated away in Atmel production when the cells are balanced. When the cells get un-balanced the CM depending offset will reappear: ATmega406 22 Voltage Reference Spike Voltage V~50mV 1 ...
Page 23
... Cell 1 and 2. age at Cell 4. The worst-case error is when Cell 1, Cell 2 and Cell 3 are balanced while Cell 4 voltage deviates from the voltage at Cell 1, 2 and 3. 18, shows the error of Cell2, Cell3 and Cell4 with 5% and 10% unbal- CM Offset with unbalanced cells. ATmega406 23 ...
Page 24
... Instantaneous and the Accumulated conversion results will be affected. The spike on VREF will be visible on 1 Accumulated Current (CADAC3…0) and 2 Instanta- neous Current (CADIC1…0) conversion results. ATmega406 24 illustrates the spike on the Voltage Reference when doing 10 temperature con- Voltage Reference Spike ...
Page 25
... Voltage Regulator Start-up sequence When powering up ATmega406 some precautions are necessary to ensure proper start-up of the Voltage Regulator. Problem Fix/Workaround The three steps below are needed to ensure proper start-up of the voltage regulator NOT connect a capacitor larger than 100 nF on the VFET pin. This is to ensure b ...
Page 26
... ATmega406 26 Updated ”Pin Configurations” on page Updated ”ADC Noise Reduction Mode” on page Updated ”Power-save Mode” on page Updated ”Power-down Mode” on page Updated ”Power-off Mode” on page Updated ”Power Reduction Register” on page Added ” ...
Page 27
... Section 9. ”Errata” on page Updated Section 9. ”Errata” on page Typos updated, bit “PSRASY” removed, CS12:0 renamed CS1[2:0]. Removed “BGEN” bit in BGCCR register. The bandgap voltage reference is always enabled in ATmega406 revision E. Updated Figure 2-1 on page 3, Figure 6-1 on page ure 21-1 on page 120 ...
Page 28
... Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI- TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT ...