PIC18F6410-I/PT Microchip Technology, PIC18F6410-I/PT Datasheet - Page 16

• Manufacturer Part Number: PIC18F6410-I/PT
• Description: IC PIC MCU FLASH 8KX16 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F6410-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 16KB (8K x 16)
• Package / Case: 64-TFQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 54
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: SPI/I2C/EUSART/AUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 54
• Number Of Timers: 4
• Operating Supply Voltage: 4.2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM183032
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12-ch x 10-bit
• Package: 64TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT64PT5 - SOCKET TRAN ICE 64MQFP/TQFPAC164319 - MODULE SKT MPLAB PM3 64TQFPDV007003 - PROGRAMMER UNIVERSAL PROMATE II
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F8410/8490/8493 FAMILY
3.5
The PIC18F8410/8490/8493 family devices do not
have
PIC18F8310/8410
Microprocessor with Boot Block mode, the locations
from 0000h to 07FFh will be internal memory. This
memory region is programmed in exactly the same
manner as the code memory (see Section 3.3 “Code
Memory Programming”).
TABLE 3-5
FIGURE 3-8:
DS39624C-page 16
Step 1: Direct access to config memory.
Step 2: Set Table Pointer for config byte to be written. Write even addresses.
Command
0000
0000
0000
0000
0000
0000
0000
0000
1111
0000
0000
1111
0000
4-Bit
any
Boot Block Programming
Boot
84 A6
8C A6
0E 30
6E F8
0E 00
6E F7
0E 00
6E F6
<LSB><MSB ignored>
00 00
2A F6
<LSB ignored><MSB>
00 00
SET ADDRESS POINTER TO CONFIGURATION LOCATION
devices
Block
CONFIGURATION PROGRAMMING FLOW
Data Payload
Hold PGC High for a
Configuration
Load Even
P9 Time
Program
Address
Done
Start
LSB
segment.
are
configured
BSF
BSF
MOVLW 30h
MOVWF TBLPTRU
MOVLW 00h
MOVWF TBLPRTH
MOVLW 00h
MOVWF TBLPTRL
Load 2 bytes and start programming
NOP - hold PGC high for time P9
INCF
Load 2 bytes and start programming
NOP - hold PGC high for time P9
When
EECON1, WREN
EECON1, CFGS
TBLPTRL
the
in
The code sequence detailed in Table 3-3 should be
used, except that the address data used in “Step 2” will
be in the range 000000h to 0007FFh.
3.6
Unlike code memory, the configuration bits are
programmed a byte at a time. The write operation
programs only 8 bits of the 16-bit payload written. The
LSB of the payload will be written to even addresses
and the MSB will be written to odd addresses. The
code
configuration locations is shown in Table 3-5.
sequence
Core Instruction
Configuration Bits Programming
Hold PGC High for a
Configuration
Load Odd
Program
P9 Time
Address
Done
MSB
Start
to
© 2007 Microchip Technology Inc.
program
two
consecutive