PIC18F4321-I/PT Microchip Technology, PIC18F4321-I/PT Datasheet - Page 390

• Manufacturer Part Number: PIC18F4321-I/PT
• Description: IC PIC MCU FLASH 4KX16 44TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F4321-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 8KB (4K x 16)
• Package / Case: 44-TQFP, 44-VQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 36
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: EUSART/I2C/MSSP/SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 36
• Number Of Timers: 4
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 13-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT44PT3 - SOCKET TRAN ICE 44MQFP/TQFPAC164305 - MODULE SKT FOR PM3 44TQFP444-1001 - DEMO BOARD FOR PICMICRO MCUAC164020 - MODULE SKT PROMATEII 44TQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F4321 FAMILY
Resets ........................................................................ 41, 253
RETFIE ............................................................................ 304
RETLW ............................................................................. 304
RETURN .......................................................................... 305
Return Address Stack ........................................................ 54
Return Stack Pointer (STKPTR) ........................................ 55
Revision History ............................................................... 377
RLCF ................................................................................ 305
RLNCF ............................................................................. 306
RRCF ............................................................................... 306
RRNCF ............................................................................. 307
S
SCK .................................................................................. 161
SDI ................................................................................... 161
SDO ................................................................................. 161
SEC_IDLE Mode ................................................................ 38
SEC_RUN Mode ................................................................ 34
Serial Clock, SCK ............................................................. 161
Serial Data In (SDI) .......................................................... 161
Serial Data Out (SDO) ..................................................... 161
Serial Peripheral Interface. See SPI Mode.
SETF ................................................................................ 307
Single-Supply ICSP Programming.
Slave Select (SS) ............................................................. 161
SLEEP .............................................................................. 308
Sleep
Software Simulator (MPLAB SIM) .................................... 324
Special Event Trigger. See Compare (CCP Mode).
Special Event Trigger. See Compare (ECCP Module).
Special Features of the CPU ............................................ 253
Special Function Registers ................................................ 62
Special ICPORT Features ................................................ 271
SPI Mode (MSSP)
SS .................................................................................... 161
SSPOV ............................................................................. 195
SSPOV Status Flag .......................................................... 195
SSPSTAT Register
Stack Full/Underflow Resets .............................................. 56
SUBFSR ........................................................................... 319
SUBFWB .......................................................................... 308
SUBLW ............................................................................ 309
DS39689E-page 388
Brown-out Reset (BOR) ........................................... 253
Oscillator Start-up Timer (OST) ............................... 253
Power-on Reset (POR) ............................................ 253
Power-up Timer (PWRT) ......................................... 253
Associated Registers ................................................. 54
OSC1 and OSC2 Pin States ...................................... 32
Map ............................................................................ 62
Associated Registers ............................................... 169
Bus Mode Compatibility ........................................... 169
Effects of a Reset ..................................................... 169
Enabling SPI I/O ...................................................... 165
Master Mode ............................................................ 166
Master/Slave Connection ......................................... 165
Operation ................................................................. 164
Operation in Power-Managed Modes ...................... 169
Serial Clock .............................................................. 161
Serial Data In ........................................................... 161
Serial Data Out ........................................................ 161
Slave Mode .............................................................. 167
Slave Select ............................................................. 161
Slave Select Synchronization .................................. 167
SPI Clock ................................................................. 166
Typical Connection .................................................. 165
R/W Bit ............................................................. 175, 177
Preliminary
SUBULNK ........................................................................ 319
SUBWF ............................................................................ 309
SUBWFB ......................................................................... 310
SWAPF ............................................................................ 310
T
Table Reads/Table Writes ................................................. 56
TBLRD ............................................................................. 311
TBLWT ............................................................................. 312
Time-out in Various Situations (table) ................................ 45
Timer0 .............................................................................. 123
Timer1 .............................................................................. 127
Timer2 .............................................................................. 133
Timer3 .............................................................................. 135
Timing Diagrams
Associated Registers ............................................... 125
Operation ................................................................. 124
Overflow Interrupt .................................................... 125
Prescaler ................................................................. 125
Prescaler Assignment (PSA Bit) .............................. 125
Prescaler Select (T0PS2:T0PS0 Bits) ..................... 125
Prescaler. See Prescaler, Timer0.
Reads and Writes in 16-Bit Mode ............................ 124
Source Edge Select (T0SE Bit) ............................... 124
Source Select (T0CS Bit) ......................................... 124
Switching Prescaler Assignment ............................. 125
16-Bit Read/Write Mode .......................................... 129
Associated Registers ............................................... 131
Interrupt ................................................................... 130
Operation ................................................................. 128
Oscillator .......................................................... 127, 129
Overflow Interrupt .................................................... 127
Resetting, Using the CCP
Special Event Trigger (ECCP) ................................. 148
TMR1H Register ...................................................... 127
TMR1L Register ....................................................... 127
Use as a Real-Time Clock ....................................... 130
Associated Registers ............................................... 134
Interrupt ................................................................... 134
Operation ................................................................. 133
Output ...................................................................... 134
PR2 Register ................................................... 144, 149
TMR2-to-PR2 Match Interrupt ......................... 144, 149
16-Bit Read/Write Mode .......................................... 137
Associated Registers ............................................... 137
Operation ................................................................. 136
Oscillator .......................................................... 135, 137
Overflow Interrupt ............................................ 135, 137
Special Event Trigger (CCP) ................................... 137
TMR3H Register ...................................................... 135
TMR3L Register ....................................................... 135
A/D Conversion ........................................................ 364
Acknowledge Sequence .......................................... 198
Asynchronous Reception ......................................... 219
Asynchronous Transmission .................................... 216
Asynchronous Transmission
Automatic Baud Rate Calculation ............................ 214
Auto-Wake-up Bit (WUE) During
Auto-Wake-up Bit (WUE) During Sleep ................... 220
Baud Rate Generator with Clock Arbitration ............ 192
BRG Overflow Sequence ......................................... 214
Layout Considerations ..................................... 130
Low-Power Option ........................................... 129
Special Event Trigger ...................................... 130
(Back to Back) ................................................. 216
Normal Operation ............................................ 220
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