PIC18F24J11-I/SS Microchip Technology, PIC18F24J11-I/SS Datasheet - Page 81

• Manufacturer Part Number: PIC18F24J11-I/SS
• Description: IC PIC MCU FLASH 16K 2V 28-SSOP
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F24J11-I/SS

• Core Size: 8-Bit
• Program Memory Size: 16KB (8K x 16)
• Core Processor: PIC
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: FLASH
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2.15 V ~ 3.6 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SSOP
• Controller Family/series: PIC18
• No. Of I/o's: 16
• Ram Memory Size: 3.6875KB
• Cpu Speed: 48MHz
• No. Of Timers: 5
• Interface: EUSART, I2C, SPI
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3776 B
• Interface Type: EUSART, I2C, SPI
• Maximum Clock Frequency: 48 MHz
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM183032, DM183022, DM183033, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 10 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164331 - MODULE SKT FOR 28SSOP 18F45J10XLT28SS-1 - SOCKET TRANSITION ICE 28SSOP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

5.3.4
The SFRs are registers used by the CPU and periph-
eral modules for controlling the desired operation of the
device. These registers are implemented as static
RAM. SFRs start at the top of data memory (FFFh) and
extend downward to occupy more than the top half of
Bank 15 (F40h to FFFh). Table 5-2, Table 5-3 and
Table 5-4 provide a list of these registers.
The SFRs can be classified into two sets: those
associated with the “core” device functionality (ALU,
Resets and interrupts) and those related to the
peripheral functions. The Reset and Interrupt registers
are described in their corresponding chapters, while the
TABLE 5-2:
© 2009 Microchip Technology Inc.
Note 1:
Address
FEDh
FECh
FFDh
FFCh
FEEh
FEBh
FEAh
FFFh
FFEh
FFBh
FFAh
FEFh
FE9h
FE8h
FE7h
FE6h
FE5h
FE4h
FE3h
FE2h
FE1h
FE0h
FF9h
FF8h
FF7h
FF6h
FF5h
FF4h
FF3h
FF2h
FF1h
FF0h
2:
3:
4:
5:
This is not a physical register.
This register is not available on 28-pin devices.
SSPxADD and SSPxMSK share the same address.
PMADDRH and PMDOUTH share the same address and PMADDRL and PMDOUTL share the same address.
PMADDRx is used in Master modes and PMDOUTx is used in Slave modes.
Reserved: Do not write to this location.
POSTDEC0
POSTDEC1
SPECIAL FUNCTION REGISTERS
POSTINC0
POSTINC1
PREINC0
PREINC1
PLUSW0
PLUSW1
TBLPTRU
TBLPTRH
TBLPTRL
INTCON2
INTCON3
STKPTR
PCLATU
PCLATH
INTCON
INDF0
INDF1
TABLAT
PRODH
PRODL
Name
FSR0H
FSR1H
FSR0L
WREG
FSR1L
TOSU
TOSH
TOSL
PCL
BSR
ACCESS BANK SPECIAL FUNCTION REGISTER MAP
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
Address
FDEh
FDDh
FDCh
FDBh
FDAh
FCEh
FCDh
FCCh
FCBh
FCAh
FDFh
FCFh
FD9h
FD8h
FD7h
FD6h
FD5h
FD4h
FD3h
FD2h
FD1h
FD0h
FC9h
FC8h
FC7h
FC6h
FC5h
FC4h
FC3h
FC2h
FC1h
FC0h
POSTDEC2
POSTINC2
SSP1ADD
PREINC2
SSP1CON1
SSP1CON2
PLUSW2
SSP1STAT
SSP1BUF
WDTCON
OSCCON
CM1CON
CM2CON
ADRESH
ADCON0
ADCON1
ADRESL
INDF2
STATUS
TMR0H
T0CON
TMR1H
T1CON
T2CON
Name
FSR2H
TMR0L
TMR1L
FSR2L
RCON
TMR2
—
PR2
(5)
(1)
(1)
(1)
(3)
(1)
(1)
Address
FBDh
FBCh
FBEh
FBBh
FBAh
FADh
FACh
FBFh
FB9h
FB8h
FB7h
FB6h
FB5h
FB4h
FB3h
FB2h
FB1h
FB0h
FAFh
FAEh
FABh
FAAh
FA9h
FA8h
FA7h
FA6h
FA5h
FA4h
FA3h
FA2h
FA1h
FA0h
CTMUCONH
CTMUCONL
PSTR1CON
PSTR2CON
CTMUICON
ECCP1DEL
ECCP2DEL
CCP1CON
CCP2CON
ECCP1AS
ECCP2AS
CCPR1H
CCPR2H
RCREG1
RCREG2
EECON2
EECON1
CCPR1L
CCPR2L
SPBRG1
TXREG1
SPBRG2
TXREG2
RCSTA1
TXSTA1
TXSTA2
Name
PIC18F46J11 FAMILY
IPR3
PIR3
IPR2
PIR2
PIE3
PIE2
ALU’s STATUS register is described later in this section.
Registers related to the operation of the peripheral
features are described in the chapter for that peripheral.
The SFRs are typically distributed among the
peripherals whose functions they control. Unused SFR
locations are unimplemented and read as ‘0’s
Note:
Address
F9Dh
F9Ch
F8Dh
F8Ch
The SFRs located between EC0h and
F5Fh are not part of the Access Bank.
Either banked instructions (using BSR) or
the MOVFF instruction should be used to
access these locations. When program-
ming in MPLAB
automatically
addressing mode.
F9Fh
F9Eh
F9Bh
F9Ah
F8Fh
F8Eh
F8Bh
F8Ah
F99h
F98h
F97h
F96h
F95h
F94h
F93h
F92h
F91h
F90h
F89h
F88h
F87h
F86h
F85h
F84h
F83h
F82h
F81h
F80h
ALRMVALH
ALRMVALL
DMACON1
DMACON2
OSCTUNE
ALRMCFG
HLVDCON
ALRMRPT
RTCVALH
PORTD
RTCVALL
PORTE
T1GCON
T3GCON
RCSTA2
Name
LATE
LATD
PORTC
PORTB
PORTA
TRISD
TRISC
TRISE
TRISB
TRISA
LATC
LATB
IPR1
PIR1
LATA
PIE1
—
(5)
(2)
(2)
(2)
(2)
®
use
Address
C18, the compiler will
F7Dh
F7Ch
F6Dh
F6Ch
F7Eh
F7Bh
F7Ah
F6Eh
F6Bh
F6Ah
F7Fh
F79h
F78h
F77h
F76h
F75h
F74h
F73h
F72h
F71h
F70h
F6Fh
F69h
F68h
F67h
F66h
F65h
F64h
F63h
F62h
F61h
F60h
the
DS39932C-page 81
PMADDRH
PMADDRL
SSP2ADD
appropriate
SSP2CON1
SSP2CON2
BAUDCON1
BAUDCON2
PMDIN1H
SSP2STAT
PMDIN1L
SSP2BUF
RXADDRH
SPBRGH1
SPBRGH2
TXADDRL
TXADDRH
RXADDRL
DMABCH
DMABCL
CMSTAT
Name
TMR3H
T3CON
T4CON
TMR3L
TMR4
PR4
—
—
—
—
—
—
(5)
(5)
(5)
(5)
(5)
(5)
(2)
(2)
(2,4)
(2,4)
(3)