PIC18F24J11-I/SS Microchip Technology, PIC18F24J11-I/SS Datasheet - Page 400

• Manufacturer Part Number: PIC18F24J11-I/SS
• Description: IC PIC MCU FLASH 16K 2V 28-SSOP
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F24J11-I/SS

• Core Size: 8-Bit
• Program Memory Size: 16KB (8K x 16)
• Core Processor: PIC
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: FLASH
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2.15 V ~ 3.6 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SSOP
• Controller Family/series: PIC18
• No. Of I/o's: 16
• Ram Memory Size: 3.6875KB
• Cpu Speed: 48MHz
• No. Of Timers: 5
• Interface: EUSART, I2C, SPI
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3776 B
• Interface Type: EUSART, I2C, SPI
• Maximum Clock Frequency: 48 MHz
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM183032, DM183022, DM183033, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 10 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164331 - MODULE SKT FOR 28SSOP 18F45J10XLT28SS-1 - SOCKET TRANSITION ICE 28SSOP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC18F46J11 FAMILY
REGISTER 25-11: WDTCON: WATCHDOG TIMER CONTROL REGISTER (ACCESS FC0h)
TABLE 25-3:
DS39932C-page 400
RCON
WDTCON
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Watchdog Timer.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
REGSLP
Name
R/W-1
2:
(2)
This bit has no effect if the Configuration bit, WDTEN, is enabled.
Not available on devices where the on-chip voltage regulator is disabled (“LF” devices).
REGSLP LVDSTAT ULPLVL
REGSLP: Voltage Regulator Low-Power Operation Enable bit
1 = On-chip regulator enters low-power operation when device enters Sleep mode
0 = On-chip regulator is active even in Sleep mode
LVDSTAT: Low-Voltage Detect Status bit
1 = V
0 = V
ULPLVL: Ultra Low-Power Wake-up Output bit (not valid unless ULPEN = 1)
1 = Voltage on RA0 > ~0.5V
0 = Voltage on RA0 < ~0.5V
Unimplemented: Read as ‘0’
DS: Deep Sleep Wake-up Status bit (used in conjunction with RCON, POR and BOR bits to determine
Reset source)
1 = If the last exit from POR was caused by a normal wake-up from Deep Sleep
0 = If the last exit from POR was a result of hard cycling V
ULPEN: Ultra Low-Power Wake-up Module Enable bit
1 = Ultra Low-Power Wake-up module is enabled; ULPLVL bit indicates comparator output
0 = Ultra Low-Power Wake-up module is disabled
ULPSINK: Ultra Low-Power Wake-up Current Sink Enable bit
1 = Ultra Low-Power Wake-up current sink is enabled (if ULPEN = 1)
0 = Ultra Low-Power Wake-up current sink is disabled
SWDTEN: Software Controlled Watchdog Timer Enable bit
1 = Watchdog Timer is on
0 = Watchdog Timer is off
LVDSTAT
IPEN
Bit 7
SUMMARY OF WATCHDOG TIMER REGISTERS
and detected, a (V
R-x
DDCORE
DDCORE
(2)
Bit 6
—
> 2.45V nominal
< 2.45V nominal
(2)
W = Writable bit
‘1’ = Bit is set
ULPLVL
R-x
DD
Bit 5
CM
< V
DSBOR
U-0
Bit 4
—
RI
—
) and (V
(2)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
DD
Bit 3
TO
DS
< V
R/W-0
DS
POR
(2)
) condition
ULPEN ULPSINK SWDTEN
Bit 2
PD
DD
(1)
, or if the Deep Sleep BOR was enabled
ULPEN
(2)
R/W-0
Bit 1
POR
© 2009 Microchip Technology Inc.
x = Bit is unknown
ULPSINK
R/W-0
Bit 0
BOR
Reset Values
SWDTEN
on Page:
R/W-0
64
64
bit 0
(1)