PIC18F14K22-I/SO Microchip Technology, PIC18F14K22-I/SO Datasheet - Page 205

• Manufacturer Part Number: PIC18F14K22-I/SO
• Description: IC PIC MCU FLASH 512KX16 20-SOIC
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F14K22-I/SO

• Program Memory Type: FLASH
• Program Memory Size: 16KB (8K x 16)
• Package / Case: 20-SOIC (7.5mm Width)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 64MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 17
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: I2C, MSSP, SPI, USART
• Maximum Clock Frequency: 64 MHz
• Number Of Programmable I/os: 17
• Number Of Timers: 4
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• A/d Bit Size: 10 bit
• A/d Channels Available: 12
• Height: 2.05 mm
• Length: 12.8 mm
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 1.8 V, 2.7 V
• Width: 7.5 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

15.4.2.3
The operation of the Synchronous Master and Slave
modes is identical (Section 15.4.1.6 “Synchronous
Master Reception”), with the following exceptions:
• Sleep
• CREN bit is always set, therefore the receiver is
• SREN bit, which is a “don't care” in Slave mode
A character may be received while in Sleep mode by
setting the CREN bit prior to entering Sleep. Once the
word is received, the RSR register will transfer the data
to the RCREG register. If the RCIE enable bit is set, the
interrupt generated will wake the device from Sleep
and execute the next instruction. If the GIE bit is also
set, the program will branch to the interrupt vector.
TABLE 15-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
 2010 Microchip Technology Inc.
BAUDCON
INTCON
IPR1
PIE1
PIR1
RCREG
RCSTA
SPBRG
SPBRGH
TXSTA
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave reception.
never Idle
Name
EUSART Synchronous Slave
Reception
EUSART Receive Register
EUSART Baud Rate Generator Register, Low Byte
EUSART Baud Rate Generator Register, High Byte
GIE/GIEH PEIE/GIEL TMR0IE
ABDOVF
CSRC
SPEN
Bit 7
—
—
—
RCIDL
ADIP
ADIE
ADIF
Bit 6
RX9
TX9
DTRXP
SREN
TXEN
RCIP
RCIE
RCIF
Bit 5
Preliminary
CKTXP
INT0IE
CREN
SYNC
TXIP
TXIE
Bit 4
TXIF
PIC18F1XK22/LF1XK22
ADDEN
SENDB
BRG16
15.4.2.4
1.
2.
3.
4.
5.
6.
7.
8.
RABIE
SSPIP
SSPIE
SSPIF
Bit 3
Set the SYNC and SPEN bits and clear the
CSRC bit. Set the TRIS bits corresponding to
the RX/DT and TX/CK I/O pins.
If using interrupts, ensure that the GIE and PEIE
bits of the INTCON register are set and set the
RCIE bit.
If 9-bit reception is desired, set the RX9 bit.
Set the CREN bit to enable reception.
The RCIF bit will be set when reception is
complete. An interrupt will be generated if the
RCIE bit was set.
If 9-bit mode is enabled, retrieve the Most
Significant bit from the RX9D bit of the RCSTA
register.
Retrieve the 8 Least Significant bits from the
receive FIFO by reading the RCREG register.
If an overrun error occurs, clear the error by
either clearing the CREN bit of the RCSTA
register or by clearing the SPEN bit which resets
the EUSART.
TMR0IF
CCP1IP
CCP1IE
CCP1IF
BRGH
FERR
Bit 2
Synchronous Slave Reception
Set-up:
—
TMR2IP
TMR2IE
TMR2IF
INT0IF
OERR
TRMT
WUE
Bit 1
TMR1IP
TMR1IE
TMR1IF
ABDEN
RABIF
RX9D
TX9D
DS41365D-page 205
Bit 0
on page
Values
Reset
259
257
260
260
260
259
259
259
259
259