PIC18F24K20-I/SS Microchip Technology, PIC18F24K20-I/SS Datasheet - Page 6

• Manufacturer Part Number: PIC18F24K20-I/SS
• Description: IC PIC MCU FLASH 8KX16 28SSOP
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F24K20-I/SS

• Program Memory Type: FLASH
• Program Memory Size: 16KB (8K x 16)
• Package / Case: 28-SSOP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 64MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 24
• Eeprom Size: 256 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: CCP/ECCP/EUSART/I2C/MSSP/SPI
• Maximum Clock Frequency: 64 MHz
• Number Of Programmable I/os: 25
• Number Of Timers: 4
• Operating Supply Voltage: 3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 11-ch x 10-bit
• Package: 28SSOP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 64 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PIC18F24/25/44/45K20
21. Module: Clocks
22. Module: Comparators
23. Module: Data EEPROM Memory
DS80366G-page 6
EC Mode operation is limited to a maximum of
48 MHz (Rev. A4 and A7 only).
Work around
Divide external clock by 4 and use HS-PLL Clock
mode for external clocking above 48 MHz.
Affected Silicon Revisions
When the CxON bit is clear, the output from the
comparator will be properly forced to zero, but the
CxPOL bit will improperly have no effect on the
CxOUT
comparator change-on-interrupt mismatch latches
as described in the data sheet.
Work around
Configure one of the unused comparator input
channels as a digital output. Use that digital output
to manipulate the comparator output to the desired
CxOUT non-interrupt level. When the comparator
is then set to the desired inputs, the mismatch
latches will be preset to the non-interrupt level and
the CxIF flag can then be cleared.
Affected Silicon Revisions
The write/erase endurance of Data EE Memory is
limited to 10K cycles.
Work around
Use error correction method that stores data in
multiple locations.
Affected Silicon Revisions
A4
A4
A4
X
X
X
A7
A7
A7
X
X
X
bit.
A9
A9
A9
X
X
This
AB
AB
AB
X
X
prevents
presetting
the
24. Module: Program Flash Memory
25. Module: Configuration Bits
26. Module: EUSART
The write/erase endurance of the PFM is limited to
1K cycles when V
degrades when V
Work around
For data tables in program Flash memory use
error correction method that stores data in multiple
locations.
Affected Silicon Revisions
Bit 3 of CONFIG3H defaults to ‘0’ after a Bulk
Erase instead of ‘1’ as specified in the data sheet.
Work around
Program the HFOFST bit to the desired state after
a Bulk Erase. All MPLAB
currently perform this way.
Affected Silicon Revisions
In Asynchronous Receive mode, the RCIDL bit of
the BAUDCON register will properly go low when
an invalid Start bit less than 1/8th of a bit time is
received. The RCIDL bit will then stay low
improperly until a valid Start bit is received.
Work around
When monitoring the RCIDL bit, measure the
length of time between the RCIDL going low and
the RCIF flag going high. If this time is greater than
one character time, then restore the RCIDL bit by
resetting the EUSART module. The EUSART
module is reset when the SPEN bit of the RCSTA
register is cleared.
Affected Silicon Revisions
A4
A4
A4
X
X
X
A7
A7
A7
X
X
X
A9
A9
A9
X
X
X
DD
© 2009 Microchip Technology Inc.
DD
AB
AB
AB
is below 3V.
X
X
X
is above 3V. Endurance
®
IDE programming tools