PIC16F723-I/SS Microchip Technology, PIC16F723-I/SS Datasheet - Page 261

• Manufacturer Part Number: PIC16F723-I/SS
• Description: IC PIC MCU FLASH 4KX14 28-SSOP
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16F723-I/SS

• Program Memory Type: FLASH
• Program Memory Size: 7KB (4K x 14)
• Package / Case: 28-SSOP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 25
• Ram Size: 192 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 11x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 192 B
• Interface Type: I2C/SCI/SPI
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 25
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 11-ch x 8-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164112 - VOLTAGE LIMITER MPLAB ICD2 VPPAC164307 - MODULE SKT FOR PM3 28SSOP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

SSP ................................................................................... 165
SSPADD Register ............................................................... 23
SSPBUF Register ............................................................... 22
SSPCON Register .............................................. 22, 172, 184
SSPEN bit ................................................................. 172, 184
SSPM bits ................................................................. 172, 184
SSPMSK Register............................................................... 23
SSPOV bit ................................................................. 172, 184
SSPSTAT Register ............................................. 23, 173, 185
STATUS Register ............................................................... 25
Synchronous Serial Port Enable bit (SSPEN)........... 172, 184
Synchronous Serial Port Mode Select bits (SSPM) .. 172, 184
T
T1CON Register ......................................................... 22, 122
T1GCON Register............................................................. 123
T2CON Register ................................................. 22, 126, 174
Thermal Considerations .................................................... 218
Time-out Sequence............................................................. 36
Timer0 ............................................................................... 109
Timer1 ............................................................................... 113
Timer2
Timers
© 2008 Microchip Technology Inc.
Associated Registers ................................................ 174
Typical Master/Slave Connection ............................. 165
I
Master Mode ............................................................. 167
SPI Mode .................................................................. 165
Typical SPI Master/Slave Connection....................... 165
TMR1ON Bit.............................................................. 123
Associated Registers ................................................ 111
Interrupt..................................................................... 111
Operation .......................................................... 109, 114
Specifications............................................................ 227
Associated registers.................................................. 124
Asynchronous Counter Mode ................................... 115
Interrupt..................................................................... 118
Modes of Operation .................................................. 114
Module On/Off (TMR1ON Bit)................................... 123
Operation During Sleep ............................................ 118
Oscillator ................................................................... 115
Prescaler................................................................... 115
Specifications............................................................ 227
Timer1 Gate
TMR1H Register ....................................................... 113
TMR1L Register........................................................ 113
Associated registers.................................................. 126
Timer1
Timer2
2
C Mode................................................................... 175
Acknowledge .................................................... 176
Addressing ........................................................ 177
Clock Stretching................................................ 182
Clock Synchronization ...................................... 183
Firmware Master Mode ..................................... 182
Hardware Setup ................................................ 175
Multi-Master Mode ............................................ 182
Reception.......................................................... 178
Sleep Operation ................................................ 183
Start/Stop Conditions ........................................ 176
Transmission .................................................... 180
Slave Mode ....................................................... 169
Reading and Writing ......................................... 115
Selecting Source............................................... 116
T1CON.............................................................. 122
T1GCON ........................................................... 123
T2CON.............................................................. 126
Preliminary
PIC16F72X/PIC16LF72X
Timing Diagrams
Timing Parameter Symbology .......................................... 219
Timing Requirements
TMR0 Register.................................................................... 22
TMR1H Register ................................................................. 22
TMR1L Register.................................................................. 22
TMR2 Register.................................................................... 22
TMRO Register................................................................... 24
TRISA ................................................................................. 52
TRISA Register............................................................. 23, 52
TRISB ................................................................................. 60
TRISB Register............................................................. 23, 61
TRISC ................................................................................. 71
TRISC Register............................................................. 23, 71
TRISD ................................................................................. 78
TRISD Register............................................................. 23, 79
TRISE ................................................................................. 82
TRISE Register............................................................. 23, 83
TXREG ............................................................................. 145
TXREG Register ................................................................. 22
TXSTA Register.......................................................... 23, 152
A/D Conversion ........................................................ 229
A/D Conversion (Sleep Mode).................................. 230
Asynchronous Reception.......................................... 150
Asynchronous Transmission .................................... 146
Asynchronous Transmission (Back-to-Back)............ 146
Brown-out Reset (BOR)............................................ 225
Brown-out Reset Situations ........................................ 35
CLKOUT and I/O ...................................................... 223
Clock Synchronization .............................................. 183
Clock Timing............................................................. 220
Enhanced Capture/Compare/PWM (ECCP)............. 228
I
I
I
I
I
INT Pin Interrupt ......................................................... 42
Reset, WDT, OST and Power-up Timer ................... 224
Slave Select Synchronization ................................... 171
SPI Master Mode...................................................... 168
SPI Master Mode (CKE = 1, SMP = 1) ..................... 232
SPI Mode (Slave Mode with CKE = 0)...................... 170
SPI Mode (Slave Mode with CKE = 1)...................... 170
SPI Slave Mode (CKE = 0) ....................................... 233
SPI Slave Mode (CKE = 1) ....................................... 233
Synchronous Reception (Master Mode, SREN) ....... 160
Synchronous Transmission ...................................... 158
Synchronous Transmission (Through TXEN) ........... 158
Time-out Sequence
Timer0 and Timer1 External Clock ........................... 227
Timer1 Incrementing Edge ....................................... 118
USART Synchronous Receive (Master/Slave) ......... 231
USART Synchronous Transmission
Wake-up from Interrupt............................................. 192
I
SPI Mode.................................................................. 234
BRGH Bit .................................................................. 154
2
2
2
2
2
2
C Bus Data............................................................. 235
C Bus Start/Stop Bits ............................................. 234
C Reception (7-bit Address)................................... 178
C Slave Mode with SEN = 0 (Reception,
C Transmission (7-bit Address) ............................. 180
C Bus Data..................................................... 236, 235
10-bit Address) ................................................. 179
Case 1 ................................................................ 37
Case 2 ................................................................ 37
Case 3 ................................................................ 37
(Master/Slave) .................................................. 230
DS41341B-page 259