tda9984a NXP Semiconductors, tda9984a Datasheet
tda9984a
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tda9984a Summary of contents
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... YCbCr compliant with ITU656 ( ITU656-like format, the input pixel clock can be made active on both edges. The TDA9984A includes a HDCP 1.2 compliant cipher block. The HDCP key are stored internally in a non-volatile OTP memory for maximum security. The TDA9984A includes a true I EDID purpose and HDCP purpose ...
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... AV receiver I Home theater I Digital video camera I Digital still camera I Personal video recorder I Media center PCs, graphic cards I Switches TDA9984A_4 Product data sheet HDMI 1.3 transmitter with 1080p upscaler embedded 2 C-bus Rev. 04 — 15 January 2009 TDA9984A © NXP B.V. 2009. All rights reserved ...
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... Input 1080p, YCbCr embedded sync, 48 kHz S/PDIF 2 channels. b) Output 1080p, YCbCr kHz S/PDIF. 5. Ordering information Table 2. Type number Package TDA9984AHW HTQFP80 [1] A lead-free package is required to comply with the new legislation. TDA9984A_4 Product data sheet HDMI 1.3 transmitter with 1080p upscaler embedded = 0 V ...
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... SSH SSA(FRO)(3V3) SSA(PLL)(3V3) SSA(PLL)(1V8) DDC_SDA DDC_SCL DDC BUS INTERRUPT 17 MASTER INT GENERATION HPD 18 HPD MANAGEMENT RxSENSE 27 TXC+ OTP 26 MEMORY TXC KEYS 30 TX0+ 29 TX0 HDCP TMDS PROCESSING SERIALIZER 33 TX1+ 32 TX1 36 TX2+ 35 TX2 24 EXT_SWING TDA9984AHW 001aag595 ...
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... OTP memory; connect to ground for digital core in normal operation 4 I audio port 7 input 5 I audio port 6 input 6 I audio port 5 input 7 I audio port 4 input 8 I audio port 3 input Rev. 04 — 15 January 2009 TDA9984A 60 V SSC 59 V DDC(1V8) 58 VPB[6] 57 VPB[7] 56 VPC[0] 55 VPC[1] 54 VPC[2] 53 ...
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... C-bus data input/output 45 P PLL analog supply voltage (1 analog ground for PLL 47 G digital ground for I/O ports Rev. 04 — 15 January 2009 TDA9984A -bus data input/output tolerant -bus clock input tolerant DDH(3V3) © NXP B.V. 2009. All rights reserved ...
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... A input bit video port A input bit video port A input bit video port A input bit video port A input bit video data enable or field reference input Rev. 04 — 15 January 2009 TDA9984A © NXP B.V. 2009. All rights reserved ...
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... YCbCr semi-planar with up to 12-bit for each component (Y, Cb and Cr) • YCbCr ITU656 with up to 12-bit data depth The TDA9984A can be set to latch data at either the rising or the falling edge. 8.1.1 Internal assignment The aim of the video input processor is to map internally the incoming data to the corresponding mode, which can be handled by the video processing ...
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... Y[7] G[6] Y[6] G[5] Y[5] G[4] Y[4] G[3] Y[3] G[2] Y[2] G[1] Y[1] G[0] Y[0] B[7] Cb[7] B[6] Cb[6] B[5] Cb[5] B[4] Cb[4] B[3] Cb[3] B[2] Cb[2] B[1] Cb[1] B[0] Cb[0] R[7] Cr[7] R[6] Cr[6] R[5] Cr[5] R[4] Cr[4] R[3] Cr[3] R[2] Cr[2] R[1] Cr[7] R[0] Cr[0] for more information concerning input format supported. Rev. 04 — 15 January 2009 TDA9984A Table semi-planar ITU656-like Y[11] YCbCr[11] Y[10] YCbCr[10] Y[9] YCbCr[9] Y[8] YCbCr[8] Y[7] YCbCr[7] Y[6] YCbCr[6] Y[5] YCbCr[5] Y[4] YCbCr[4] Y[3] YCbCr[3] Y[2] YCbCr[2 Y[1] YCbCr[1] Y[0] YCbCr[0] CbCr[11] - CbCr[10] - CbCr[9] - CbCr[8] - CbCr[7] - CbCr[6] - CbCr[5] - CbCr[4] - CbCr[3] - CbCr[2] - CbCr[1] ...
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Table 5. Inputs of video input formatter Space color Format Channels Sync RGB 8-bit external embedded YCbCr 8-bit external embedded YCbCr ...
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... R[6] G[7] VPC[7] R[7] B [7:0] B [7:0] B [7: [7:0] G [7:0] G [7: [7:0] R [7:0] R [7: Rev. 04 — 15 January 2009 TDA9984A Control Pin RGB HSYNC/HREF used VSYNC/VREF used DE/FREF used ... B [7:0] B [7:0] xxx xxx ... G [7:0] G [7:0] xxx xxx ... R [7:0] R [7:0] xxx xxx 001aag380 © NXP B.V. 2009. All rights reserved. ...
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... Cr[6] Y[7] VPC[7] Cr[7] Cb [7:0] Cb [7:0] Cb [7: [7:0] Y [7:0] Y [7: [7:0] Cr [7:0] Cr [7: Rev. 04 — 15 January 2009 TDA9984A Control Pin YCbCr HSYNC/HREF used VSYNC/VREF used DE/FREF used ... Cb [7:0] Cb [7:0] xxx xxx ... Y [7:0] Y [7:0] xxx xxx ... Cr [7:0] Cr [7:0] xxx xxx 001aag381 © NXP B.V. 2009. All rights reserved. ...
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... Y [3] VPB[3] Cb[ VPB[4] Cb[ VPB[5] Cb[ VPB[6] Cb[10] Y [10] Cr[10 VPB[7] Cb[11] Y [11] Cr[11 [11:0] Cr [11: Rev. 04 — 15 January 2009 TDA9984A Control Pin Cr[4] Y [4] HSYNC/HREF used 1 Cr[5] Y [5] VSYNC/VREF used 1 Cr[6] Y [6] DE/FREF 1 Cr[7] Y [7] 1 Cr[8] Y [8] 1 Cr[9] Y [9] 1 [10] 1 [11] 1 [11:0] ... Cr [11:0] Y xxx ...
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... Y [3] VPB[3] Cb[ VPB[4] Cb[ VPB[5] Cb[ VPB[6] Cb[10] Y [10] Cr[10 VPB[7] Cb[11] Y [11] Cr[11 [11:0] Cr [11: Rev. 04 — 15 January 2009 TDA9984A Control Pin Cr[4] Y [4] HSYNC/HREF 1 Cr[5] Y [5] VSYNC/VREF 1 Cr[6] Y [6] DE/FREF 1 Cr[7] Y [7] 1 Cr[8] Y [8] 1 Cr[9] Y [9] 1 [10] 1 [11] 1 [11:0] ... Cr [11:0] Y xxx YCbCr ...
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... VPB[3] Cb[ VPB[4] Cb[ VPB[5] Cb[ VPB[6] Cb[10] Y [10] Cr[10 VPB[7] Cb[11] Y [11] Cr[11 [11:0] Cr [11:0] Y [11: Rev. 04 — 15 January 2009 TDA9984A Control Pin YCbCr Cr[4] Y [4] HSYNC/HREF not used 1 Cr[5] Y [5] VSYNC/VREF not used 1 Cr[6] Y [6] DE/FREF not used 1 Cr[7] Y [7] 1 Cr[8] Y [8] 1 Cr[ [10 ...
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... VPB[3] Cb[ VPB[4] Cb[8] Y [8] 0 VPB[5] Cb[9] Y [9] 0 VPB[6] Cb[10] Y [10] 0 VPB[7] Cb[11] Y [11 [11:0] Cr [11:0] Y [11: Rev. 04 — 15 January 2009 TDA9984A Control Pin Cr[4] Y [4] HSYNC/HREF not used 1 Cr[5] Y [5] VSYNC/VREF not used 1 Cr[6] Y [6] DE/FREF 1 Cr[7] Y [7] 1 Cr[8] Y [8] 1 Cr[9] Y [9] 1 Cr[10] Y [10] 1 Cr[11] Y [11] 1 ... ...
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... Y [10] VPC[6] Cb[10 [11] Y [11] VPC[7] Cb[11 [11:0] Y [11:0] Y [11: [11:0] Cb [11:0] Cr [11: Rev. 04 — 15 January 2009 TDA9984A Control Pin YCbCr Cr[4] HSYNC/HREF used Cr[5] VSYNC/VREF used Cr[6] DE/FREF used Cr[7] Cr[8] Cr[9] Cr[10] Cr[11] Y [11:0] Y [11:0] ... [11:0] Cr [11:0] ... 4 4 © NXP B.V. 2009. All rights reserved. 001aag386 ...
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... Y [9] VPC[ [10] Y [10] VPC[ [11] Y [11] VPC[ [11:0] Y [11:0] Y [11: [11:0] Cb [11:0] Cr [11: Rev. 04 — 15 January 2009 TDA9984A Control YCbCr Pin semi-planar Cb[4] Cr[4] HSYNC/HREF not used Cb[5] Cr[5] VSYNC/VREF not used Cb[6] Cr[6] DE/FREF Cb[7] Cr[7] Cb[8] Cr[8] Cb[9] Cr[9] Cb[10] Cr[10] Cb[11] Cr[11] Y [11:0] Y [11:0] ... [11:0] Cr [11:0] ... 4 4 © NXP B.V. 2009. All rights reserved. ...
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... C-bus register. 8.1.4 Input and output video format Due to the flexible video input formatter, the TDA9984A can accept a large range of inputs formats. This flexibility allows the TDA9984A to be compatible with the maximum number of MPEG decoders. Moreover, these input formats may be changed in many ways (space color converter, upsampler and scaler transmitted across the HDMI link ...
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... All upscaling modes are available only for YCbCr input format. 12-bit) data stream format can be upsampled into an 8-bit) data stream by repeating or linearly interpolating the Rev. 04 — 15 January 2009 TDA9984A VIDEO STANDARD OUTPUT (1) (2) (3) (2) (1) (2) (1) (4) ...
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... ENA_APx and GND_APx on page 00h (both audio inputs and clock input as well). 8.2.1 S/PDIF The audio port AP6 is used for this feature. In this format, the TDA9984A supports 2-channel uncompressed PCM data (IEC 60958) layout 0, or compressed bit stream multi-channels (Dolby Digital, DTS, AC3, etc.) layout 1. ...
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... NXP Semiconductors The TDA9984A is able to recover the original clock from the S/PDIF signal (no need of external clock). In addition, it can also use an external clock to decode the S/PDIF signal. 2 8.2.2 I S-bus There are 4 carrying eight uncompressed audio channels. The S-bus signal including serial data in, word select and serial clock. Various I formats are supported and can be selected by setting the appropriate bits of the register ...
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... C-bus. As the keys are stored internally, the security is maximized. 8.3.1.1 Repeater function The TDA9984A can be used in a repeater device according to the HDCP specification, Rev 1.2 . The TDA9984A is able to store the KSV list of a maximum of 127 devices in a register memory. 8.3.1.2 SHA-1 To deal with repeater, a SHA-1 calculation is performed by the transmitter and by the downstream repeater ...
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... TMDS output buffers The TMDS output amplitude can be adjusted via an external resistor connected between pins EXT_SWING and strongly recommended to use R 500 mV. By doing so, the TDA9984A shall meet the minimum low-level output voltage as per HDMI specification, Rev 1.3a table 4-15. TDA9984A_4 Product data sheet HDMI 1 ...
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... Pixel repetition To transmit video formats with pixel rates below 25 mega samples per second or to increase the number of audio sample packets in each frame, the TDA9984A uses pixel repetition to increase the number of pixels sent by the frame. The pixel clock is multiplied by the same factor as given in Table 16 ...
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... Pin HPD is the hot plug detect pin input tolerant. When asserted, the hot plug detect signal tells the transmitter that the receiver is connected. When changing from LOW to HIGH, the TDA9984A has to read EDID to match the video format to the format the receiver can handle. ...
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... The block can be read by the microprocessor to determine the supported video and audio format of the downstream side. Remark: When the block is read by the TDA9984A, it generates an interrupt to warn the main processor that the TDA9984A is ready to transmit the content. Once the content is read-out by the microprocessor, it can allow reading other blocks if required ...
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... A0 and A1 (see Table 18. Device address The I C-bus access format is shown in Firstly, the master writes the TDA9984A address and the subaddress to access the specific register, and then the data. Fig 16 C-bus registers definitions 9.1 Memory page management 2 ...
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... NXP Semiconductors • TDA9984AHW will have the value 1000 XXXX The four LSBs are used for indicating the die version. 10. Limiting values Table 20. In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol V DD(3V3) V DD(1V8 stg T amb esd 11 ...
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... C to +85 C; typical values are measured amb Conditions pF pF +85 C; typical values are measured amb Conditions R = 610 EXT_SWING Rev. 04 — 15 January 2009 TDA9984A Min Typ [1][3] - 500 [1][2] - 742 [1][4] - 320 [1][3] - 630 [1][2] - 872 [1][4] - 450 - 30 Min Typ - - 2 ...
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... +85 C; typical values are measured amb Conditions pin VCLK pin VCLK 2 channels pin AP5 (MCLK) pin AP5 (MCLK) Standard-mode Fast-mode Standard-mode Fast-mode Rev. 04 — 15 January 2009 TDA9984A = 25 C; unless amb Min Typ Max Unit 150 - - MHz ...
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... VCLK VPA[7:0] VPB[7:0] VPC[7:0] t su(D) Data is not allowed to change in the shaded area. YCbCr (semi-planar) Cb[0] Y [0] 0 Cb[1] Y [1] 0 Cb[2] Y [2] 0 Cb[3] Y [3] 0 Cb[4] Cb[0] Cb[5] Cb[1] Cb[6] Cb[2] Cb[7] Cb[3] Rev. 04 — 15 January 2009 TDA9984A t t su(D) h( su(D) h( h(D) su( (ITU656-like) Y [0] Cb[ [1] Cb[ [2] Cb[ ...
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... Y[4] Y [ Y[5] Y [ Y[6] Y [10] Y [10 Y[7] Y [11] Y [11 Cr[0] Cb[4] Cr[4] Cr[1] Cb[5] Cr[5] Cr[2] Cb[6] Cr[6] Cr[3] Cb[7] Cr[7] Cr[4] Cb[8] Cr[8] Cr[5] Cb[9] Cr[9] Cr[6] Cb[10] Cr[10] Cr[7] Cb[11] Cr[11] Rev. 04 — 15 January 2009 TDA9984A [ (ITU656-like) Cb[4] Y [4] Cr[ Cb[5] Y [5] Cr[ Cb[6] Y [6] Cr[ Cb[7] Y [7] Cr[ Cb[8] Y [8] Cr[ Cb[9] Y [9] Cr[ Cb[10] Y [10] Cr[10] Y [10] ...
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... NXP Semiconductors 13.2 Timing parameters for supported video The TDA9984A supports all EIA/CEA-861B standards and ATSC video input formats. Table 27. Timing parameters for EIA/CEA-861B Format Format V frequency (Hz) 59.94 Hz systems 1 (VGA) 640 480p 59.9401 2, 3 720 480p 59.9401 4 1280 720p 59.9401 5 1920 1080i 59 ...
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... Rev. 04 — 15 January 2009 TDA9984A Pixel frequency Pixel (MHz) repetition 54.000 4 54.000 2 148.50 1 Pixel frequency Pixel (MHz) repetition 74.250 1 74.175 1 74.250 1 74 ...
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... scale (1) ( 0.20 12.1 4.79 12.1 4.79 0.5 0.09 11.9 4.69 11.9 4.69 REFERENCES JEDEC JEITA MS-026 Rev. 04 — 15 January 2009 TDA9984A detail 14.15 14.15 0.75 1 0.2 0.08 13.85 13.85 0.45 EUROPEAN PROJECTION SOT841 (1) ...
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... Phase-Locked Loop Start Active Video Secure Hash Algorithm 1 Sony/Philips Digital Interface Transition Minimized Differential Signalling Vertical Horizontal REFerence Vertical REFerence Vertical SYNChronization Y = luminance Chroma component blue Chroma component red Rev. 04 — 15 January 2009 TDA9984A © NXP B.V. 2009. All rights reserved ...
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... Table 20, Table 22, Table 23, Table 24 Product data sheet Preliminary data sheet Objective data sheet Rev. 04 — 15 January 2009 TDA9984A Change notice Supersedes TDA9984A_3 in Cb and for consistency B R and Table 25: changed the temperature min - TDA9984A_2 - TDA9984_1 - - © NXP B.V. 2009. All rights reserved. ...
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... Arques Avenue Suite 100, Sunnyvale CA 94085, USA, e-mail: admin@hdmi.org. 17.5 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners C-bus — logo is a trademark of NXP B.V. http://www.nxp.com salesaddresses@nxp.com Rev. 04 — 15 January 2009 TDA9984A © NXP B.V. 2009. All rights reserved ...
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... Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2009. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com TDA9984A All rights reserved. Date of release: 15 January 2009 Document identifier: TDA9984A_4 ...