IDT70V3389S Integrated Device Technology, IDT70V3389S Datasheet

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IDT70V3389S

Manufacturer Part Number
IDT70V3389S
Description
High-speed 3.3v 64k X 18 Synchronous Pipelined Dual-port Static Ram With 3.3v Or 2.5v Interface
Manufacturer
Integrated Device Technology
Datasheet

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additional logic
©2001 Integrated Device Technology, Inc.
R/W
CE
CE
True Dual-Port memory cells which allow simultaneous
access of the same memory location
High-speed clock to data access
– Commercial: 4.2/5/6ns (max.)
– Industrial: 5/6ns (max)
Pipelined output mode
Counter enable and reset features
Dual chip enables allow for depth expansion without
Full synchronous operation on both ports
– 7.5ns cycle time, 133MHz operation (9.6 Gbps bandwidth)
– Fast 4.2ns clock to data out
– 1.8ns setup to clock and 0.7ns hold on all control, data, and
UB
OE
LB
0L
1L
L
L
L
L
CLK
I/O
L
CNTRST
CNTEN
0 L
A
- I/O
ADS
A
15L
0L
L
1 7 L
L
L
Counter/
Address
Reg.
HIGH-SPEED 3.3V 64K x 18
SYNCHRONOUS PIPELINED
DUAL-PORT STATIC RAM
WITH 3.3V OR 2.5V INTERFACE
Dout0-8_L
Dout9-17_L
Din_L
ADDR_L
B
W
0
L
B
W
1
L
MEMORY
1
64K x 18
ARRAY
– Data input, address, byte enable and control registers
– Self-timed write allows fast cycle time
Separate byte controls for multiplexed bus and bus
matching compatibility
LVTTL- compatible, single 3.3V (±150mV) power supply for
core
LVTTL- compatible, selectable 3.3V (±150mV)/2.5V (±125mV)
power supply for I/Os and control signals on each port
Industrial temperature range (-40°C to +85°C) is
available for selected speeds
Available in a 128-pin Thin Quad Plastic Flatpack (TQFP),
208-pin fine pitch Ball Grid Array, and 256-pin Ball
Grid Array
Dout9-17_R
Dout0-8_R
B
W
1
R
ADDR_R
address inputs @ 133MHz
B
W
0
R
Din_R
Counter/
Address
Reg.
IDT70V3389S
4832 tbl 01
DSC 4832/8
A
CNTRST
CNTEN
I/O
A
ADS
OE
UB
LB
R/ W
CE
CE
15R
0R
0R
R
R
0R
1R
R
R
- I/O
R
CLK
R
R
17R
R
.

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IDT70V3389S Summary of contents

Page 1

... Ball Grid Array, and 256-pin Ball Grid Array Dout0-8_L Dout0-8_R Dout9-17_L Dout9-17_R 64K x 18 MEMORY ARRAY Din_L Din_R ADDR_L ADDR_R 1 IDT70V3389S I/O - I/O 0R 17R CLK R A 15R Counter Address CNTRST R Reg. ADS R ...

Page 2

... IDT70V3389S High-Speed 64K x 18 Dual-Port Synchronous Pipelined Static RAM The IDT70V3389 is a high-speed 64K x 18 bit synchronous Dual-Port RAM. The memory array utilizes Dual-Port memory cells to allow simultaneous access of any address from both ports. Registers on control, data, and address inputs provide minimal setup and hold times. The timing latitude provided by this approach allows systems to be designed with very short cycle times ...

Page 3

... IDT70V3389S High-Speed 64K x 18 Dual-Port Synchronous Pipelined Static RAM I I I/O I 10R 10L DDQL I/O NC I/O V 11L 11R DDQL ...

Page 4

... IDT70V3389S High-Speed 64K x 18 Dual-Port Synchronous Pipelined Static RAM A 14L A 15L DDQL 10L IO 10R V DDQR 11L IO 11R IO 12L IO 12R 13R IO 13L IO 14R IO 14L IO 15R IO 15L V DDQL 16R IO 16L V DDQR V SS ...

Page 5

... IDT70V3389S High-Speed 64K x 18 Dual-Port Synchronous Pipelined Static RAM Left Port Right Port Chip Enables , , R/W R/W Read/Write Enable Output Enable Address 0L 15L 0R 15R I/O - I/O I/O - I/O Data Input/Output 0L 17L 0R 17R CLK CLK Clock L R ADS ADS ...

Page 6

... IDT70V3389S High-Speed 64K x 18 Dual-Port Synchronous Pipelined Static RAM Previous Addr Address Address Used CLK NOTES: 1. "H" "L" "X" = Don't Care. IH, IL, 2. Read and write operations are controlled by the appropriate setting of R/ ...

Page 7

... IDT70V3389S High-Speed 64K x 18 Dual-Port Synchronous Pipelined Static RAM Symbol Parameter Conditions C Input Capacitance V IN (3) C Output Capacitance V OUT NOTES: 1. These parameters are determined by device characterization, but are not production tested. 2. 3dV references the interpolated capacitance when the input and output switch from from ...

Page 8

... IDT70V3389S High-Speed 64K x 18 Dual-Port Synchronous Pipelined Static RAM Sym bol Param eter CE and CE I Dynam ic Ope rating DD L Current (Bo th Outputs Disab led , (1) P orts A ctive ) MAX tand by Current SB1 L (1) ( orts - TTL MAX Inp uts ) ...

Page 9

... IDT70V3389S High-Speed 64K x 18 Dual-Port Synchronous Pipelined Static RAM Input Pulse Levels (Address & Controls) Input Pulse Levels (I/Os) Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load 50 DATA OUT Figure 1. AC Output Test load tCD (Typical, ns) ...

Page 10

... IDT70V3389S High-Speed 64K x 18 Dual-Port Synchronous Pipelined Static RAM Symbol Parameter t Clock Cycle Time (Pipelined) CYC2 t Clock High Time (Pipelined) CH2 t Clock Low Time (Pipelined) CL2 t Clock Rise Time R t Clock Fall Time F t Address Setup Time SA t Address Hold Time ...

Page 11

... IDT70V3389S High-Speed 64K x 18 Dual-Port Synchronous Pipelined Static RAM t CYC2 t CH2 CLK UB, LB (0- (4) ADDRESS An (1 Latency) DATA OUT (1) OE NOTES asynchronously controlled; all other inputs are synchronous to the rising clock edge. ...

Page 12

... IDT70V3389S High-Speed 64K x 18 Dual-Port Synchronous Pipelined Static RAM CLK R ADDRESS L MATCH DATA VALID INL t CO CLK R R ADDRESS R MATCH DATA OUTR NOTES UB, LB, and ADS = V , CNTEN, and CNTRST = V ...

Page 13

... IDT70V3389S High-Speed 64K x 18 Dual-Port Synchronous Pipelined Static RAM t CYC2 t t CH2 CL2 CLK UB (3) An ADDRESS DATA IN (1) DATA OUT OE READ NOTES: 1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals. ...

Page 14

... IDT70V3389S High-Speed 64K x 18 Dual-Port Synchronous Pipelined Static RAM t CYC2 t t CH2 CL2 CLK ADDRESS (3) INTERNAL (7) An ADDRESS t t SAD HAD ADS CNTEN DATA IN WRITE EXTERNAL ADDRESS t CYC2 t t CH2 CL2 CLK ADDRESS (3) INTERNAL Ax ADDRESS ADS ...

Page 15

... LOW on CE for one clock cycle will power down 0 1 the internal circuitry to reduce static power consumption. Multiple chip enables allow easier banking of multiple IDT70V3389s for depth expan- sion configurations. Two cycles are required with CE HIGH to re-activate the outputs ...

Page 16

... IDT70V3389S High-Speed 64K x 18 Dual-Port Synchronous Pipelined Static RAM IDT XXXXX A 99 Device Power Speed Type A A Package Process/ Temperature Range Blank I BF PRF 70V3389 1Mbit (64K x 18-Bit) Synchronous Dual-Port RAM 6.42 16 Industrial and Commercial Temperature Ranges Commercial (0°C to +70°C) Industrial (-40° ...

Page 17

... IDT70V3389S High-Speed 64K x 18 Dual-Port Synchronous Pipelined Static RAM 1/18/99: Initial Public Release 3/15/99: Page 9 Additional notes 4/28/99: Added fpBGA paclage 6/8/99: Page 2 Changed package body height from 1.5mm to 1.4mm 6/15/99: Page 5 Deleted note 6 for Table II 7/14/99: Page 2 Corrected pin 8/4/99: Page 6 Improved power numbers 10/1/99: Upgraded speed to 133MHz, added 2.5V I/O capability ...

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