adc1613d NXP Semiconductors, adc1613d Datasheet
adc1613d
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adc1613d Summary of contents
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... The device also includes a SPI programmable full-scale to allow flexible input voltage range from (peak-to-peak). Excellent dynamic performance is maintained from the baseband to input frequencies of 170 MHz or more, making the ADC1613D ideal for use in communications, imaging, and medical applications. 2. Features and benefits SNR, 72.5 dBFS ...
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... ADC1613D105HN/C1 105 ADC1613D080HN/C1 80 ADC1613D065HN/C1 65 ADC1613D_SER_2 Preliminary data sheet ADC1613D series; serial JESD204A interface Package Name Description HVQFN56 plastic thermal enhanced very thin quad flat package; no leads; 56 terminals; body 8 × 8 × 0.85 mm HVQFN56 plastic thermal enhanced very thin quad flat package; no leads; 56 terminals; body 8 × 8 × 0.85 mm HVQFN56 plastic thermal enhanced very thin quad flat package ...
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... STAGE INAM CLKP DLL PLL CLKM INBP T/H INPUT STAGE INBM ADC1613D Fig 1. Block diagram ADC1613D_SER_2 Preliminary data sheet ADC1613D series; serial JESD204A interface SDIO/DCS CFG ( SCLK/DCS CS ERROR SPI CORRECTION AND DIGITAL PROCESSING ADCA CORE 16-BIT D15 to D0 PIPELINED OTR 8-bit ...
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... All information provided in this document is subject to legal disclaimers. Rev. 02 — 23 April 2010 ADC1613D series ADC1613D series; serial JESD204A interface 42 DGND 41 DGND 40 VDDD 39 CMLPA 38 CMLNA 37 VDDD 36 DGND ADC1613D 35 DGND 34 VDDD 33 CMLNB 32 CMLPB ...
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... All information provided in this document is subject to legal disclaimers. Rev. 02 — 23 April 2010 ADC1613D series ADC1613D series; serial JESD204A interface Description channel B analog input analog power supply 3 V analog power supply 3 V SPI clock data format select SPI data IO duty cycle stabilizer ...
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... All information provided in this document is subject to legal disclaimers. Rev. 02 — 23 April 2010 ADC1613D series ADC1613D series; serial JESD204A interface Description reference programming pin voltage reference input/output analog power supply 3 V Min − ...
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... SPI: pins CS, SDIO/DCS, and SCLK/DCS V LOW-level input voltage IL V HIGH-level input voltage IH I LOW-level input current IL I HIGH-level input current IH C input capacitance I ADC1613D_SER_2 Preliminary data sheet ADC1613D series; serial JESD204A interface Conditions Min 2.85 1. 125 Msps; - clk f =70 MHz 125 Msps; - clk MHz ...
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... LOW-level output OL voltage V HIGH-level output OH voltage Output levels 1.8 V; SWING_SEL[2:0] = 011 DDD V LOW-level output OL voltage V HIGH-level output OH voltage ADC1613D_SER_2 Preliminary data sheet ADC1613D series; serial JESD204A interface Conditions Min −5 track mode track mode - track mode - track mode 0.9 - peak-to-peak output 0.5 input 0 coupled ...
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... Minimum and maximum values are across the full temperature = 1 DDD amb (INAP, INBP) − 1 DDA DDD I All information provided in this document is subject to legal disclaimers. Rev. 02 — 23 April 2010 ADC1613D series ADC1613D series; serial JESD204A interface Min Typ Max - ...
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... ADC1613D125 Unit Typ Max Min Typ Max dBc dBc dBc dBc dBc dBc dBc dBc dBc ...
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... Typ Max Min Typ Max - 100 - - 100 - = 25 °C. Minimum and maximum values are across the full temperature range T amb ADC1613D105 ADC1613D125 Unit Min Typ Max Min Typ Max - dBc - dBc - dBc - dBc - 100 ...
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... Minimum and maximum values are across the full temperature range T amb ADC1613D105 ADC1613D125 Unit Min Typ Max Min Typ Max 75 - 105 100 - 125 Msps clock cycle ...
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... Eye diagram receiver common-mode Eye diagram receiver common-mode All information provided in this document is subject to legal disclaimers. Rev. 02 — 23 April 2010 ADC1613D series ADC1613D series; serial JESD204A interface Figure 3 and Figure 4. Test conditions © NXP B.V. 2010. All rights reserved. ...
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... w(SCLK) h SCLK SDIO W1 W0 R/W SPI timings All information provided in this document is subject to legal disclaimers. Rev. 02 — 23 April 2010 ADC1613D series ADC1613D series; serial JESD204A interface Min Typ °C. Minimum and maximum values are = 1 ...
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... NXP Semiconductors 13. Application information 13.1 Analog inputs 13.1.1 Input stage description The analog input of the ADC1613D supports differential or single-ended input drive. Optimal performance is achieved using differential inputs with the common-mode input voltage (V The full scale analog input voltage range is configurable between 1 V (p-p) and 2 V (p-p) ...
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... Figure 8 would be suitable for a baseband application. 100 nF ADT1-1WT Analog input 100 nF Single transformer configuration All information provided in this document is subject to legal disclaimers. Rev. 02 — 23 April 2010 ADC1613D series ADC1613D series; serial JESD204A interface R INAP INBP C R INAM INBM 005aaa176 ...
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... System reference and power management 13.2.1 Internal/external reference The ADC1613D has a stable and accurate built-in internal reference voltage to adjust the ADC full-scale. This reference voltage can be set internally via SPI or with pins VREF an SENSE (see and −6 dB, via SPI control bits INTREF[2:0] (when bit INTREF_EN = 1; see ...
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... All information provided in this document is subject to legal disclaimers. Rev. 02 — 23 April 2010 ADC1613D series ADC1613D series; serial JESD204A interface EXT_ref BANDGAP REFERENCE EXT_ref ADC CORE SENSE pin VREF pin GND 330 pF capacitor to GND VREF pin = SENSE pin and ...
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... Reference SPI gain control Level 0 dB −1 dB −2 dB −3 dB −4 dB −5 dB −6 dB not used All information provided in this document is subject to legal disclaimers. Rev. 02 — 23 April 2010 ADC1613D series ADC1613D series; serial JESD204A interface VREF 330 pF REFERENCE EQUIVALENT SCHEMATIC SENSE 005aaa117 VREF 330 pF REFERENCE EQUIVALENT ...
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... INAM, INBM, INAP, and INBP) must be between 0.9 V and 2 V for optimal performance. 13.3 Clock input 13.3.1 Drive modes The ADC1613D can be driven differentially (SINE, LVPECL or LVDS) with little or no influence on dynamic performances. It can also be driven by a single-ended LVCMOS signal connected to pin CLKP (CLKM should be connected to ground via a capacitor). a. Rising edge LVCMOS Fig 16 ...
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... Package ESD CLKP CLKM All information provided in this document is subject to legal disclaimers. Rev. 02 — 23 April 2010 ADC1613D series ADC1613D series; serial JESD204A interface Sine clock input b. Sine clock input (with transformer) LVPECL clock input d. LVPECL clock input Figure 18. The common-mode ...
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... If single-ended is implemented without setting SE_SEL accordingly, the unused pin should be connected to ground via a capacitor. 13.3.3 Clock input divider The ADC1613D contains an input clock divider that divides the incoming clock by a factor of 2 (when bit CLKDIV = 1; see clock frequency with better jitter performance, leading to a better SNR result once acquisition has been performed ...
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... N' = N+CS CF: position of controls bits S samples per frame cycle HD: frame boundary break Padding with Tails bits (TT) Mx(N'xS) bits Fig 21. General overview of the JESD204A serializer ADC1613D_SER_2 Preliminary data sheet ADC1613D series; serial JESD204A interface VDDD 50 Ω CMLPA/CMLPB CMLNA/CMLNB − LANES FRAME ...
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... All information provided in this document is subject to legal disclaimers. Rev. 02 — 23 April 2010 ADC1613D series ADC1613D series; serial JESD204A interface LANE_MODE[1:0] 00 SCR 8-bit 10-bit 01 ...
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... Serial Peripheral Interface (SPI) 13.6.1 Register description The ADC1613D serial interface is a synchronous serial communications port allowing for easy interfacing with many industry microprocessors. It provides access to the registers that control the operation of the chip in both read and write modes. This interface is configured as a 3-wire type (SDIO as bidirectional pin). ...
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... ADC1613D_SER_2 Preliminary data sheet Instruction bytes All information provided in this document is subject to legal disclaimers. Rev. 02 — 23 April 2010 ADC1613D series ADC1613D series; serial JESD204A interface Register N (data) Register (data ...
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Table 17. Register allocation map [1] Addr Register name R/W Bit definition Hex Bit 7 Bit 6 ADC control register 0003 Channel index R/W - 0005 Reset and R/W SW_RST Operating modes 0006 Clock R/W - 0008 Vref R/W - ...
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Table 17. Register allocation map …continued [1] Addr Register name R/W Bit definition Hex Bit 7 Bit 6 0821 Cfg_1_BID R/W* 0 0822 Cfg_3_SCR_L R/W* SCR 0823 Cfg_4_F R/W* 0 0824 Cfg_5_K R/W* 0 0825 Cfg_6_M R/W* 0 0826 Cfg_7_CS_N ...
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... DIFF_SE R CLKDIV2_SEL R/W 0 DCS_EN R/W ADC1613D_SER_2 Preliminary data sheet ADC1613D series; serial JESD204A interface Value Description 111111 not used ADCB will get the next SPI command: 0 ADCB not selected 1 ADCB selected ADCA will get the next SPI command: 0 ADCA not selected 1 ADCA selected ...
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... Value Description 00000000 custom digital test pattern (bit All information provided in this document is subject to legal disclaimers. Rev. 02 — 23 April 2010 ADC1613D series ADC1613D series; serial JESD204A interface +31 LSB ... 0 ... −32 LSB © NXP B.V. 2010. All rights reserved ...
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... Symbol Access 7 SW_RST R FSM_SW_RST R ADC1613D_SER_2 Preliminary data sheet ADC1613D series; serial JESD204A interface Value Description 00000 custom digital test pattern (bit 000 not used Value Description 0 set to 1 when a synchronization error occurs 110 reserved 0 not used 0 power-on-reset ...
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... Differential mode 1 synchronization input mode is set in Single-ended mode R 1 not used All information provided in this document is subject to legal disclaimers. Rev. 02 — 23 April 2010 ADC1613D series ADC1613D series; serial JESD204A interface [2] [2] [2] [2] [2] [2] [2] [2] © NXP B.V. 2010. All rights reserved. ...
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... Access Value Description R/W 11111111 defines the initialization vector for the scrambler polynomial (upper) All information provided in this document is subject to legal disclaimers. Rev. 02 — 23 April 2010 ADC1613D series ADC1613D series; serial JESD204A interface © NXP B.V. 2010. All rights reserved ...
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... Access Value Description R 0000000 not used R/W * defines the number of converters per device, minus 1 All information provided in this document is subject to legal disclaimers. Rev. 02 — 23 April 2010 ADC1613D series ADC1613D series; serial JESD204A interface © NXP B.V. 2010. All rights reserved ...
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... JEDEC Standard No.204A) All information provided in this document is subject to legal disclaimers. Rev. 02 — 23 April 2010 ADC1613D series ADC1613D series; serial JESD204A interface © NXP B.V. 2010. All rights reserved ...
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... PRSB generator (PRBS type is defined with “PRBS_TYPE” (Ser_PRBS_ctrl register) All information provided in this document is subject to legal disclaimers. Rev. 02 — 23 April 2010 ADC1613D series ADC1613D series; serial JESD204A interface © NXP B.V. 2010. All rights reserved ...
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... R 000 not used R/W ADC power-down control: 0 ADC is operational 1 ADC is in Power-down mode All information provided in this document is subject to legal disclaimers. Rev. 02 — 23 April 2010 ADC1613D series ADC1613D series; serial JESD204A interface © NXP B.V. 2010. All rights reserved ...
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... R 000 not used R/W ADC power-down control: 0 ADC is operational 1 ADC is in Power-down mode All information provided in this document is subject to legal disclaimers. Rev. 02 — 23 April 2010 ADC1613D series ADC1613D series; serial JESD204A interface © NXP B.V. 2010. All rights reserved ...
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... 8.1 5.95 8.1 6.55 8.0 5.80 8.0 6.40 0.5 6.5 6.5 7.9 5.65 7.9 6.25 References JEDEC JEITA - - - MO-220 All information provided in this document is subject to legal disclaimers. Rev. 02 — 23 April 2010 ADC1613D series ADC1613D series; serial JESD204A interface detail 0.5 0.4 0.1 0.05 0.05 0.1 0.3 European projection SOT684-7 c sot684-7_po ...
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... Preliminary data sheet • Product status changed from Objective to Preliminary 20100413 Objective data sheet All information provided in this document is subject to legal disclaimers. Rev. 02 — 23 April 2010 ADC1613D series ADC1613D series; serial JESD204A interface Change Supersedes notice - ADC1613D_SER_1 - - © NXP B.V. 2010. All rights reserved. ...
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... Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. All information provided in this document is subject to legal disclaimers. Rev. 02 — 23 April 2010 ADC1613D series ADC1613D series; serial JESD204A interface © NXP B.V. 2010. All rights reserved ...
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... For sales office addresses, please send an email to: ADC1613D_SER_2 Preliminary data sheet ADC1613D series; serial JESD204A interface NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ ...
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... Register description . . . . . . . . . . . . . . . . . . . . 29 13.6.3.1 ADC control registers . . . . . . . . . . . . . . . . . . . 29 13.6.4 JESD204A digital control registers . . . . . . . . . 31 14 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 39 15 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 40 16 Legal information 16.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 41 ADC1613D series; serial JESD204A interface 16.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 16.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 41 16.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 42 17 Contact information . . . . . . . . . . . . . . . . . . . . 42 18 Contents I(cm) Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘ ...