adc1412d NXP Semiconductors, adc1412d Datasheet
adc1412d
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adc1412d Summary of contents
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... ADC. The device also includes an SPI programmable full-scale to allow a flexible input voltage range (peak-to-peak). With excellent dynamic performance from the baseband to input frequencies of 170 MHz or more, the ADC1412D is ideal for use in communications, imaging and medical applications. ...
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... ADC CORE INPUT 14-BIT STAGE PIPELINED INBM ERROR CORRECTION AND DIGITAL PROCESSING All information provided in this document is subject to legal disclaimers. Rev. 03 — 6 August 2010 ADC1412D series CMOS or LVDS DDR digital outputs SDIO/ODS SCLK/DFS CS SPI INTERFACE OTRA CMOS: DA13 to DA0 OUTPUT or DRIVERS ...
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... I complementary clock input 10 G analog ground 11 O bottom reference; channel top reference; channel B All information provided in this document is subject to legal disclaimers. Rev. 03 — 6 August 2010 ADC1412D series CMOS or LVDS DDR digital outputs ADC1412D 40 HVQFN64 39 38 ...
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... data output bit 10; channel data output bit 11; channel A All information provided in this document is subject to legal disclaimers. Rev. 03 — 6 August 2010 ADC1412D series CMOS or LVDS DDR digital outputs …continued © NXP B.V. 2010. All rights reserved ...
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... REFBT 13 VCMB AGND 14 INBM 15 INBP 16 Transparent top view Pin configuration with LVDS/DDR digital outputs selected All information provided in this document is subject to legal disclaimers. Rev. 03 — 6 August 2010 ADC1412D series CMOS or LVDS DDR digital outputs …continued HVQFN64 39 38 ...
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... DA12 and DA13 multiplexed, true O differential output data DA12 and DA13 multiplexed, complement Table 2). All information provided in this document is subject to legal disclaimers. Rev. 03 — 6 August 2010 ADC1412D series CMOS or LVDS DDR digital outputs [1] © NXP B.V. 2010. All rights reserved ...
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... CMOS mode; f clk MHz i LVDS DDR mode 125 Msps; f clk i All information provided in this document is subject to legal disclaimers. Rev. 03 — 6 August 2010 ADC1412D series CMOS or LVDS DDR digital outputs Min −0.4 −0.4 −0.4 −55 −40 - Conditions [1] [1] Min Typ 2 ...
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... I = <tbd> <tbd> OH 3-state; output level = 0 V 3-state; output level = V high impedance; see I = <tbd> OL All information provided in this document is subject to legal disclaimers. Rev. 03 — 6 August 2010 ADC1412D series CMOS or LVDS DDR digital outputs Min Typ - 1200 - 1100 - 855 - 795 - ± ...
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... °C and 1 DDO amb = 1 DDA DDO All information provided in this document is subject to legal disclaimers. Rev. 03 — 6 August 2010 ADC1412D series CMOS or LVDS DDR digital outputs Min Typ 0.8V - DDO - 1.2 - 350 - <tbd> −5 ...
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... ADC1412D105 ADC1412D125 Unit Min Typ Max Min Typ Max dBc dBc dBc dBc dBc dBc dBc dBc dBc ...
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... ADC1412D105 ADC1412D125 Unit Min Typ Max Min Typ Max - dBc - dBc - dBc - dBc - 100 - - 100 - dBc = −40 °C to +85 °C amb ADC1412D105 ADC1412D125 Min Typ Max Min Typ Max 75 - 105 100 - 125 - 14 ...
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... pF; minimum and maximum values are across the full temperature range T amb L − −1 dBFS; unless otherwise specified. INBP INBM ADC1412D105 ADC1412D125 Unit Min Typ Max Min Typ Max - 4.2 - ...
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... DAVP DAVM t clk LVDS DDR mode timing All information provided in this document is subject to legal disclaimers. Rev. 03 — 6 August 2010 ADC1412D series CMOS or LVDS DDR digital outputs − 13) (N − 12) (N − 11 clk − 13) (N − 12) (N − ...
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... CS w(SCLK) h SCLK SDIO W1 W0 R/W SPI timing All information provided in this document is subject to legal disclaimers. Rev. 03 — 6 August 2010 ADC1412D series CMOS or LVDS DDR digital outputs Conditions Min Typ data to SCLK HIGH SCLK HIGH 5 - data to SCLK HIGH ...
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... NXP Semiconductors 11. Application information 11.1 Device control The ADC1412D can be controlled via the Serial Peripheral Interface (SPI control mode) or directly via the I/O pins (Pin control mode). 11.1.1 SPI and Pin control modes The device enters Pin control mode at power-up and remains in this mode as long as pin CS is held HIGH ...
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... HIGH, two’s complement is selected. 11.2 Analog inputs 11.2.1 Input stage The analog input of the ADC1412D supports a differential or a single-ended input drive. Optimal performance is achieved using differential inputs with the common-mode input voltage (V The full-scale analog input voltage range is configurable between 1 V (p-p) and 2 V (p-p) ...
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... ADT1-1WT 100 nF Analog input 100 nF Figure 11 is recommended for high frequency applications. In All information provided in this document is subject to legal disclaimers. Rev. 03 — 6 August 2010 ADC1412D series CMOS or LVDS DDR digital outputs R INAP/INBP C R INAM/INBM 005aaa093 C (pF) 12 ...
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... System reference and power management 11.3.1 Internal/external references The ADC1412D has a stable and accurate built-in internal reference voltage to adjust the ADC full-scale. This reference voltage can be set internally via SPI or with pins VREF and SENSE (programmable steps between 0 dB and −6 dB via control bits INTREF when bit INTREF_EN = logic 1 ...
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... DDA 15) 1 pin VREF connected to pin SENSE and 16) via 330 pF capacitor to AGND All information provided in this document is subject to legal disclaimers. Rev. 03 — 6 August 2010 ADC1412D series CMOS or LVDS DDR digital outputs BANDGAP REFERENCE EXT_ref ADC CORE VREF pin 330 pF capacitor to AGND ...
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... Fig 16. Internal reference via SPI (p- (p-p) to Figure 16 illustrate how to connect the SENSE and VREF pins to select the All information provided in this document is subject to legal disclaimers. Rev. 03 — 6 August 2010 ADC1412D series CMOS or LVDS DDR digital outputs VREF 330 pF REFERENCE ...
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... O(cm) Package ESD 1.5 V 0.1 μ pins INAP/INBP and INAM/INBM should be I(cm) for optimal performance and should always be between 0.9 V DDA All information provided in this document is subject to legal disclaimers. Rev. 03 — 6 August 2010 ADC1412D series CMOS or LVDS DDR digital outputs Full-scale (p- 1.78 V 1.59 V 1.42 V 1. ...
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... NXP Semiconductors 11.4 Clock input 11.4.1 Drive modes The ADC1412D can be driven differentially (SINE, LVPECL or LVDS) with little or no degradation on dynamic performance. It can also be driven by a single-ended Low Voltage Complementary Metal Oxide Semiconductor (LVCMOS) signal connected to pin CLKP (pin CLKM should be connected to ground via a capacitor) or CLKM (pin CLKP should be connected to ground via a capacitor) ...
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... Clock input divider The ADC1412D contains an input clock divider that divides the incoming clock by a factor of 2 (when bit CLKDIV = logic 1; see higher clock frequency with better jitter performance, leading to a better SNR result once acquisition has been performed ...
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... V to 3.3 V compatibility and is isolated from the ADC core. DDO 50 Ω LOGIC DRIVER All information provided in this document is subject to legal disclaimers. Rev. 03 — 6 August 2010 ADC1412D series CMOS or LVDS DDR digital outputs Parasitics ESD Package 005aaa057 © NXP B.V. 2010. All rights reserved. ...
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... DAn_DAn + 1_M; DBn_DBn + 1_M − + OGND Table LVDS DDR output register 2 All information provided in this document is subject to legal disclaimers. Rev. 03 — 6 August 2010 ADC1412D series CMOS or LVDS DDR digital outputs 100 Ω 005aaa112 Figure 23 100 Ω RECEIVER 005aaa113 32) in order to adjust the output logic voltage ...
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... However possible to add a digital offset to the output code via the SPI (bits DIG_OFFSET; see 11.5.6 Test patterns For test purposes, the ADC1412D can be configured to transmit one of a number of predefined test patterns (via bits TESTPAT_SEL; see be defined by the user (TESTPAT_USER; see when TESTPAT_SEL = 101. The selected test pattern is transmitted regardless of the analog input ...
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... Serial Peripheral Interface (SPI) 11.6.1 Register description The ADC1412D serial interface is a synchronous serial communications port that allows easy interfacing with many commonly used microprocessors. It provides access to the registers that control the operation of the chip. This interface is configured as a 3-wire type (SDIO as bidirectional pin). ...
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... During circuit initialization it does not matter which output data standard has been selected. At power-up, the device enters Pin control mode. A falling edge on CS triggers a transition to SPI control mode. When the ADC1412D enters SPI control mode, the output data standard (CMOS/LVDS DDR) is determined by ...
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... SDIO (CMOS LVDS DDR) CS SDIO (CMOS LVDS DDR) All information provided in this document is subject to legal disclaimers. Rev. 03 — 6 August 2010 ADC1412D series CMOS or LVDS DDR digital outputs Offset binary, LVDS DDR default mode at start-up 005aaa063 two's complement, CMOS default mode at start-up 005aaa064 © ...
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Register allocation map Table 19. Register allocation map Addr Register name R/W Bit definition (Hex) Bit 7 Bit 6 0003 Channel index R/W 0005 Reset and R/W SW_ operating mode RST 0006 Clock R/W - 0008 Internal reference R/W ...
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... R/W clock input divide disabled 1 enabled R/W duty cycle stabilizer 0 disabled 1 enabled All information provided in this document is subject to legal disclaimers. Rev. 03 — 6 August 2010 ADC1412D series CMOS or LVDS DDR digital outputs © NXP B.V. 2010. All rights reserved ...
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... LSB, vice versa) R/W output data format 00 offset binary 01 two’s complement 10 gray code 11 offset binary All information provided in this document is subject to legal disclaimers. Rev. 03 — 6 August 2010 ADC1412D series CMOS or LVDS DDR digital outputs © NXP B.V. 2010. All rights reserved ...
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... All information provided in this document is subject to legal disclaimers. Rev. 03 — 6 August 2010 ADC1412D series CMOS or LVDS DDR digital outputs © NXP B.V. 2010. All rights reserved ...
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... R/W drive strength for data CMOS output buffer 00 low 01 medium 10 high 11 very high All information provided in this document is subject to legal disclaimers. Rev. 03 — 6 August 2010 ADC1412D series CMOS or LVDS DDR digital outputs © NXP B.V. 2010. All rights reserved ...
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... All information provided in this document is subject to legal disclaimers. Rev. 03 — 6 August 2010 ADC1412D series CMOS or LVDS DDR digital outputs © NXP B.V. 2010. All rights reserved ...
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... 9.1 7.25 9.1 7.25 9.0 7.10 9.0 7.10 0.5 7.5 7.5 8.9 6.95 8.9 6.95 References JEDEC JEITA - - - - - - All information provided in this document is subject to legal disclaimers. Rev. 03 — 6 August 2010 ADC1412D series CMOS or LVDS DDR digital outputs detail 0.5 0.4 0.1 0.05 0.05 0.1 0.3 European projection SOT804 sot804-3_po ...
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... Figure 12 “Reference equivalent schematic” • Dynamic characteristics table Objective data sheet Objective data sheet All information provided in this document is subject to legal disclaimers. Rev. 03 — 6 August 2010 ADC1412D series CMOS or LVDS DDR digital outputs Change Supersedes notice ADC1412D065_080_105_125_2 has been updated (Table 7) has been updated ...
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... Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. All information provided in this document is subject to legal disclaimers. Rev. 03 — 6 August 2010 ADC1412D series CMOS or LVDS DDR digital outputs © NXP B.V. 2010. All rights reserved ...
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... Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. http://www.nxp.com salesaddresses@nxp.com All information provided in this document is subject to legal disclaimers. Rev. 03 — 6 August 2010 ADC1412D series CMOS or LVDS DDR digital outputs © NXP B.V. 2010. All rights reserved ...
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... NXP B.V. 2010. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com ADC1412D series CMOS or LVDS DDR digital outputs All rights reserved. Date of release: 6 August 2010 Document identifier: ADC1412D_SER ...