CA3096AE Intersil, CA3096AE Datasheet - Page 13
CA3096AE
Manufacturer Part Number
CA3096AE
Description
IC TRANS ARRAY NPN/PNP 16-DIP
Manufacturer
Intersil
Datasheet
1.CA3096CE.pdf
(15 pages)
Specifications of CA3096AE
Rohs Status
RoHS non-compliant
Typical Performance Curves
Metallization Mask Layout
40
30
20
10
0
0
10
4-10 (0.102-0.254)
(0.940-1.143)
37-45
20
30
6
5
4
3
2
1
0
FIGURE 39. CAPACITANCE vs BIAS VOLTAGE (PNP)
40
0
(0.940-1.143)
CA3096, CA3096A, CA3096C
(Continued)
37-45
1
2
3
C
BIAS VOLTAGE (V)
BC
CA3096H
4
C
BE
13
basic inch dimensions as indicated. Grid graduations are in mils (10
Dimensions in parentheses are in millimeters and are derived from the
inch).
The photographs and dimensions represent a chip when it is part of
the wafer. When the wafer is cut into chips, the cleavage angles are
57 degrees instead of 90 degrees with respect to the face of the chip.
Therefore, the isolated chip is actually 7mils (0.17mm) larger in both
dimensions.
5
6
C
BI
7
8
9
10
-3