CA5130E Intersil, CA5130E Datasheet - Page 6

• Manufacturer Part Number: CA5130E
• Description: MOSFET INPUT/C-MOS OUTPUT
• Manufacturer: Intersil

Specifications of CA5130E

• Rohs Status: RoHS non-compliant
• Other names: CA5130

Application Information
Circuit Description
The input terminals shown in the block diagram of the CA5130
Series CMOS Operational Amplifiers may be operated down to
0.5V below the negative supply rail, and the output can be
swung very close to either supply rail in many applications.
Consequently, the CA5130 Series circuits are ideal for single
supply operation. Three Class A amplifier stages, having the
individual gain capability and current consumption shown in the
Block Diagram, provide the total gain of the CA5130. A biasing
circuit provides two potentials for common use in the first and
second stages. Terminal 8 can be used both for phase
compensation and to strobe the output stage into quiescence.
When Terminal 8 is tied to the negative supply rail (Terminal 4)
by mechanical or electrical means, the output potential at
Terminal 6 essentially rises to the positive supply rail potential
at Terminal 7. This condition of essentially zero current drain in
the output stage under the strobed “OFF” condition can only be
achieved when the ohmic load resistance presented to the
amplifier is very high (e.g., when the amplifier output is used to
drive CMOS digital circuits in comparator applications).
Input Stages
The circuit of the CA5130 is shown in the Schematic Diagram.
It consists of a differential input stage using PMOS field-effect
transistors (Q
transistors (Q
with resistors R
function as a differential-to-single-ended converter to provide
base drive to the second stage bipolar transistor (Q
nulling, when desired, can be effected by connecting a
100,000 potentiometer across Terminals 1 and 5 and the
potentiometer slider arm to Terminal 4. Cascode connected
PMOS transistors Q
the input stage. The biasing circuit for the constant current
source is subsequently described. The small diodes D
through D
transients, e.g., including static electricity during handling for
Q
Second Stage
Most of the voltage gain in the CA5130 is provided by the
second amplifier stage, consisting of bipolar transistor Q
and its cascode connected load resistance provided by
PMOS transistors Q
for these PMOS transistors is subsequently described.
Miller-Effect compensation (roll-off) is accomplished by
simply connecting a small capacitor between Terminals 1
and 8. A 47pF capacitor provides sufficient compensation for
stable unity gain operation in most applications.
Bias Source Circuit
At total supply voltages, somewhat above 8.3V, resistor R
and zener diode Z
across the series connected circuit, consisting of resistor R
diodes D
6
and Q
1
7
8
.
through D
provide gate oxide protection against high voltage
6
9
, Q
, Q
3
through R
7
10
1
) working into a mirror pair of bipolar
) functioning as load resistors together
2
serve to establish a voltage of 8.3V
3
4
, Q
, and PMOS transistor Q
and Q
4
are the constant current source for
6
. The mirror pair transistors also
5
. The source of bias potentials
6
1
. A tap at the
11
CA5130, CA5130A
). Offset
5
11
2
1
,
junction of resistor R
potential of about 4.5V for PMOS transistors Q
respect to Terminal 7. A potential of about 2.2V is developed
across diode connected PMOS transistor Q
Terminal 7 to provide gate bias for PMOS transistors Q
Q
Q
identical, the approximately 200 A current in Q
a similar current in Q
for both the first and second amplifier stages, respectively.
At total supply voltages somewhat less than 8.3V, zener diode
Z
across series connected R
variations in supply voltage. Consequently, the gate bias for Q
Q
variations. This variation results in deterioration of the power
supply rejection ratio (PSRR) at total supply voltages below
8.3V. Operation at total supply voltages below about 4.5V
results in seriously degraded performance.
Output Stage
The output stage consists of a drain loaded inverting amplifier
using CMOS transistors operating in the Class A mode. When
operating into very high resistance load, the output can be
swung within mV of either supply rail. Because the output stage
is a drain loaded amplifier, its gain is dependent upon the load
impedance. The transfer characteristics of the output stage for
a load returned to the negative supply rail are shown in Figure
15. Typical op amp loads are readily driven by the output stage.
Because large signal excursions are nonlinear, requiring
feedback for good waveform reproduction, transient delays may
be encountered. As a voltage follower, the amplifier can achieve
0.01% accuracy levels, including the negative supply rail.
Input Current Variation with Common Mode Input
Voltage
As shown in the Table of Electrical Specifications, the input
current for the CA5130 Series Op Amps is typically 5pA at
T
potential of +7.5V with respect to negative supply Terminal 4.
Figure 24 contains data showing the variation of input current
as a function of common mode input voltage at T
data shows that circuit designers can advantageously exploit
these characteristics to design circuits which typically require
an input current of less than 1pA, provided the common mode
input voltage does not exceed 2V. As previously noted, the
input current is essentially the result of the leakage current
through the gate protection diodes in the input circuit and,
therefore, a function of the applied voltage. Although the finite
resistance of the glass terminal-to-case insulator of the metal
can package also contributes an increment of leakage current,
there are useful compensating factors. Because the gate
protection network functions as if it is connected to Terminal 4
potential, and the metal can case of the CA5130 is also
internally tied to Terminal 4, input Terminal 3 is essentially
“guarded” from spurious leakage currents.
A
1
3
2
5
. It should be noted that Q
becomes nonconductive and the potential, developed
= 25
and Q
and Q
o
C when Terminals 2 and 3 are at a common mode
2
3
, Q
. Since transistors Q
3
varies in accordance with supply voltage
1
2
and diode D
and Q
1
, D
3
1
1
-D
as constant current sources
is “mirror connected” to both
1
, Q
4
, and Q
4
2
provides a gate bias
, Q
3
1
are designed to be
, varies directly with
1
with respect to
A
4
1
= 25
and Q
establishes
o
C. This
5
2
with
and
4
,