MAX17009GTL+ Maxim Integrated Products, MAX17009GTL+ Datasheet - Page 41

• Manufacturer Part Number: MAX17009GTL+
• Description: IC CTLR VIDEO SERIAL DUAL 40TQFN
• Manufacturer: Maxim Integrated Products

Specifications of MAX17009GTL+

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 7. SVI Send Byte Address Description
Table 8. Serial VID 8-Bit Data Field Encoding
The MAX17009 controller has a minimum on-time,
which determines the maximum input operating voltage
that maintains the selected switching frequency. With
higher input voltages, each pulse delivers more energy
than the output is sourcing to the load. At the beginning
of each cycle, if the output voltage is still above the
feedback threshold voltage, the controller does not trig-
ger an on-time pulse, resulting in pulse-skipping opera-
tion. This allows the controller to maintain regulation
above the maximum input voltage, but forces the con-
troller to effectively operate with a lower switching fre-
quency. This results in an input threshold voltage at
which the controller begins to skip pulses (V
BITS
BITS
6:4
6:0
3
2
1
0
7
Always 110b
X = don’t care
V
the VID for V
mode (GNDS2 = V
V
the VID for V
unified VDD in combined mode
V
contains the VID for V
PSI_L: Power-Save Indicator:
• 0 means the processor is at an optimal load
• 1 means the processor is at a high current-
SVID[6:0] as defined in Table 7.
DAC2
DAC1
DAC_NB
V
and the regulator(s) can enter power-saving
mode. Offset is disabled if previously enabled
through the OPTION pin. The MAX17009 enters
1-phase operation if in combined mode
(GNDS2 = H).
consumption state. Offset is enabled if
previously enabled through the OPTION pin.
The MAX17009 returns to 2-phase operation if
in combined mode (GNDS2 = H).
IN SKIP
(
, if set, then the following data byte contains
, if set, then the following data byte contains
______________________________________________________________________________________
, if set then the following data byte
)
=
DAC2
DAC1
V
OUT
; bit 2 is ignored in combined
DESCRIPTION
DESCRIPTION
in separate mode, and the
DDIO
⎛
⎜
⎝
DAC_NB
f
Maximum Input Voltage
SW ONMIN
)
AMD Mobile Serial VID Dual-Phase
t
1
⎞
⎟
⎠
IN(SKIP)
Fixed-Frequency Controller
):
where f
the OSC resistor, and t
driver’s turn-on delay (DL low to DH high). For the best
high-voltage performance, use the slowest switching
frequency setting (100kHz per phase, R
Careful PCB layout is critical to achieve low switching
losses and clean, stable operation. The switching
power stage requires particular attention (Figure 13). If
possible, mount all the power components on the top
side of the board with their ground terminals flush
against one another, and mount the controller and ana-
log components on the bottom layer so the internal
ground layers shield the analog components from any
noise generated by the power components. Follow
these guidelines for good PCB layout:
•
•
•
•
•
•
Keep the high-current paths short, especially at the
ground terminals. This is essential for stable, jitter-
free operation.
Connect all analog grounds to a separate solid cop-
per plane, then connect the analog ground to the
GND pins of the controller. The following sensitive
components connect to analog ground: V
and REF bypass capacitors, remote-sense and
GNDS bypass capacitors, and the resistive connec-
tions (ILIM, OSC, TIME).
Keep the power traces and load connections short.
This is essential for high efficiency. The use of thick
copper PCBs (2oz vs. 1oz) can enhance full-load
efficiency by 1% or more. Correctly routing PCB
traces is a difficult task that must be approached in
terms of fractions of centimeters, where a single mΩ
of excess trace resistance causes a measurable
efficiency penalty.
Connections for current limiting (CSP_, CSN_) and
voltage positioning (FBS, GNDS) must be made
using Kelvin-sense connections to guarantee the
current-sense accuracy. Place current-sense filter
capacitors and voltage-positioning filter capacitors
as close to the IC as possible.
Route high-speed switching nodes and driver
traces away from sensitive analog areas (REF, V
FBAC, FBDC, etc.). Make all pin-strap control input
connections (SHDN, PGD_IN, OPTION) to analog
ground or V
Route the high-speed serial-interface signals (SVC,
SVD) in parallel, keeping the trace lengths identical.
Keep the SVC and SVD away from the high-current
switching paths.
SW
is the per-phase switching frequency set by
CC
rather than power ground or V
ONMIN
PCB Layout Guidelines
is 185ns (max) minus the
OSC
= 432kΩ).
CC
, V
DD
DDIO
.
CC
41
,
,