FS-953 Digi International, FS-953 Datasheet - Page 31
![no-image](/images/manufacturer_photos/0/1/193/digi_international_sml.jpg)
FS-953
Manufacturer Part Number
FS-953
Description
JTAG-BOOSTER FOR ADSP-21XXX 3.3V
Manufacturer
Digi International
Series
Digi/FS Forthr
Type
FLASHr
Datasheet
1.FS-953.pdf
(69 pages)
Specifications of FS-953
Contents
Programmer and Associated Interface Software
For Use With/related Products
ADI ADSP-21xxx, 3.3V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- Current page: 31 of 69
- Download datasheet (189Kb)
FLAG10
FLAG11
PWM_EVENT1 Inp
PWM_EVENT0 Inp
SDCLK1
// The direction of each following pin can be set independent of the others,
// but this pins can not be read back.
REDY
DT0_A
DT0_B
DT1_A
DT1_B
EMU#
// The following pin has an open drain output with a weak pull up.
// The pin is bidirectional.
CPA#
// The following pins are output only pins.
// Setting to input (tristate) one of these pins results in an error.
BMSTR
// The following pins are input only.
// Setting to output of one of these pins results in an error.
// Declaration of the direction of these pins is optional.
IRQ0#
IRQ1#
IRQ2#
BSEL
RESET#
ID0
ID1
CLKIN
CS#
DR0_A
DR0_B
DR1_A
DR1_B
HBR#
DMAR1#
DMAR2#
SBTS#
JTAG_ADSP-21xxxa.doc
Inp
Inp
Out,Lo
Inp
Out,Lo
Out,Lo
Out,Lo
Out,Lo
Inp
Inp
Out,Hi
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
// Flag Pin
// Flag Pin
// PWM output/event capture
// PWM output/event capture
// SDRAM clock output
// Host Bus Acknowledge
// Data Transmit
// Data Transmit
// Data Transmit
// Data Transmit
// Emulation Status
// Core Priority Access
// Bus Master Output
// Interrupt Request
// Interrupt Request
// Interrupt Request
// EPROM Boot Select, BSEL=1 -> Boot from EPROM
// Processor Reset
// Multiprocessing ID
// Multiprocessing ID
// Clock In
// Chip Select Input
// Data Receive
// Data Receive
// Data Receive
// Data Receive
// Host Bus Request
// DMA Request 1, DMA Channel 7
// DMA Request 2, DMA Channel 8
// Suspend Bus Three-State
31
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