FS-9003 Digi International, FS-9003 Datasheet - Page 32
FS-9003
Manufacturer Part Number
FS-9003
Description
JTAG-BOOSTER FOR XSCALE 3.3V
Manufacturer
Digi International
Series
Digi/FS Forthr
Type
FLASHr
Datasheet
1.FS-9003.pdf
(89 pages)
Specifications of FS-9003
Contents
Programmer and Associated Interface Software
For Use With/related Products
Intel XScale, 3.3V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- Current page: 32 of 89
- Download datasheet (208Kb)
Sample File JTAG255.INI:
// Description file for Intel PXA255/26x
Target: Generic Target
// Adapt this file carefully to your design!!
// All chip select signals are set to output and inactive.
// The chip selects for the external PC-Card are set to output and inactive.
// All signals should be defined. Undefined signals are set to their defaults.
// Pin names are defined in upper case.
// Low active signal are signed with a trailing #.
// The following pins are complete bidirectional pins.
// The direction of each pin can be set independent of the other pins.
// Each pin can be used as an input.
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
GPIO20
GPIO21
GPIO22
GPIO23
GPIO24
GPIO25
GPIO26
GPIO27
32
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Out,Hi // CS1#, chip select 1
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
//
// GP_RST#, GPreset input
//
//
//
//
// MMCCLK, MMC clock output
// 48MHZ, 48MHz clock output
// MMCCS0, MMC chip select 0
// MMCCS1, MMC chip select 1
// USB_RCV, USB client single-ended interface RCV
// RTCCLK, RTC 1Hz output
// 3.6MHZ, 3.6MHz clock output
// 32KHZ, 32kHz clock output
// MBGNT, memory controller grant
// MBREQ, memory controller alternate bus master request
// PWM0, PMW0 output
// PWM1, PWM1 output
// RDY, ext. bus ready input
// DREQ1, ext. DMA request 1
// DREQ0, ext. DMA request 0
//
//
// SSPSCLK, SSP clock output
// SSPSFRM, SSP frame
// SSPTXD, SSP transmit data
// SSPRXD, SSP receive data
// SSPEXTCLK, SSP ext. clock input
JTAG_XScaleb.doc
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