SW500009 Microchip Technology, SW500009 Datasheet - Page 78

• Manufacturer Part Number: SW500009
• Description: HI-TECH FOR DSPIC/PIC24
• Manufacturer: Microchip Technology
• Type: Compilerr
• Series: PIC24 & DsPICr

Specifications of SW500009

• Supported Families: PIC24
• Core Architecture: PIC, DsPIC
• Software Edition: Standard
• Kit Contents: Software And Docs
• Tool Type: Compiler
• Mcu Supported Families: PIC24 MCUs And DsPIC DSCs
• Lead Free Status / RoHS Status: Not applicable / RoHS Compliant
• For Use With/related Products: DSPIC3X/PIC24
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 025; 778-1003; 778-1003

Interrupt Handling in C
will be placed at the interrupt vector. Any registers or objects to be saved are done so to areas of
memory especially reserved for this purpose.
located in Bank 0. If the processor for which the code is written has more than one RAM bank, it is
impossible to swap to Bank 0 without corrupting W, so an intsave_n psect is allocated to each RAM
bank (where n represents the bank number). The addresses of these memory areas are identical in
the lower seven bits.When the interrupt occurs, W will be saved into one of these memory areas
depending on the bank in which the processor was in before the interrupt occurred.
resides in Bank 0.
locations. If these are used during the interrupt function, they too will be saved by separate routines
which are automatically linked.
3.10.1.5 High-End Context Saving
The ALUSTA, BSR and PCLATH registers are automatically saved by code in a psect called intcode.
This code is placed at the interrupt vector. This code includes a jump to the users interrupt code. If
the interrupt function uses the W register, this will also be saved before the jump is taken. These
registers are saved to an unbanked area of RAM so that it does not matter which RAM bank is
selected when the interrupt occurs.
3.10.1.6 Context Restoration
Any objects saved by the compiler are automatically restored before the interrupt function returns.
3.10.1.7 Interrupt Levels
Normally it is assumed by the compiler that any interrupt may occur at any time, and an error will
be issued by the linker if a function appears to be called by an interrupt and by main-line code, or
another interrupt. Since it is often possible for the user to guarantee this will not happen for a specific
routine, the compiler supports an interrupt level feature.
able, and any interrupt functions at the same level will be assumed by the compiler to be mutually
exclusive. (Since the midrange PIC devices only support one active interrupt there is no value in
using more than one interrupt level when these processors are selected.) This exclusion must be
guaranteed by the user - the compiler is not able to control interrupt priorities. Each interrupt routine
may be assigned a single level, either 0 or 1.
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If context saving is required, this is performed by code placed in to a psect called intentry which
If the W register is to be saved, it is stored to memory reserved in the intsave_0 psect which is
If the STATUS register is to be saved, it is stored into memory reserved in the intsave psect which
Some C code, for example division, may call an assembly routine which used temporary RAM
This is achieved with the #pragma interrupt_level directive. There are two interrupt levels avail-
C Language Features