DO-CPLD-DK-J-G Xilinx Inc, DO-CPLD-DK-J-G Datasheet - Page 22

• Manufacturer Part Number: DO-CPLD-DK-J-G
• Description: KIT STARTER CPLD JAPANESE
• Manufacturer: Xilinx Inc
• Series: CoolRunner™- IIr
• Type: CPLD Development Kitr

Specifications of DO-CPLD-DK-J-G

• Contents: Proto Board, Download Cable, Software and Documentation
• For Use With/related Products: CoolRunner-ll, XC9500XL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Power, Sequencing, and Slew Rates
22
I/O Standards
Simultaneous Switching Output Limits
Decoupling Guidelines
Schmitt Trigger
The following is sample code for how to achieve the fast rise in VHDL:
Code for Verilog:
The supported I/O standards for the different CPLD families are as follows:
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•
•
Xilinx does not characterize the CPLD device packages to estimate the maximum number
of Simultaneous Switching Outputs (SSOs) before ground bounce. However, Xilinx
recommends that you not have more than 8 SSOs on the entire chip (all banks included).
If you need to have more than 8 SSOs, Xilinx recommends that you consider altering the
slew rate setting on these outputs to skew the outputs relative to each other. By following
this recommendation, you can avoid ground bounce due to SSOs.
The minimum decoupling recommendations for CPLD devices are to provide both 0.1 and
0.01 uF capacitors at every V
ground.
CoolRunner-II is the only family to have the Schmitt trigger feature. A Schmitt trigger is an
input circuit used to reduce noise on the input signal. In CoolRunner-II devices, there is a
Schmitt trigger available on all I/Os, but only with the I/O standards that do not require a
VREF.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity top is
end top;
architecture Behavioral of top is
begin
end Behavioral;
module top(data, data_to_pin );
assign data_to_pin = ((data & data_to_pin) == 0)? data : 1'bz;
endmodule
XC9500, XC9500XL, and XC9500XV: LVTTL, LVCMOS33
CoolRunner XPLA3: LVCMOS33
CoolRunner-II: LVTTL, LVCMOS33, LVCMOS25, LVCMOS18, LVCMOS15, HSTL_1,
SSTL2_1, SSTL3_1, and LVCMOS15 require use of Schmitt trigger inputs.
data_to_pin<= data
Port ( data : in std_logic;
input data;
inout data_to_pin ;
www.xilinx.com
CC
when ((data and data_to_pin) ='0') else 'Z';
point of the chip and attach them directly to the nearest
data_to_pin : inout std_logic);
UG445 (v1.1) November 27, 2007
CPLD I/O User Guide
R