MPC5553EVB Freescale Semiconductor, MPC5553EVB Datasheet - Page 44
MPC5553EVB
Manufacturer Part Number
MPC5553EVB
Description
KIT EVAL MPC5553MZP132
Manufacturer
Freescale Semiconductor
Type
Microcontrollerr
Datasheet
1.MPC5553EVBE.pdf
(68 pages)
Specifications of MPC5553EVB
Contents
Eval Board and Demo Software
Processor To Be Evaluated
MPC55xx
Data Bus Width
32 bit
Interface Type
RS-232, Ethernet
For Use With/related Products
MPC5553
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Electrical Characteristics
3.13.9
44
1
2
Spec
SS timing specified at V
varies depending on track delays, master pad delays, and slave pad delays.
FCK duty cycle is not 50% when it is generated through the division of the system clock by an odd number.
2
3
4
5
6
7
8
External device data sample at
FCK period (t
Clock (FCK) high time
Clock (FCK) low time
SDS lead / lag time
SDO lead / lag time
EQADC data setup time (inputs)
EQADC data hold time (inputs)
EQADC data sample at
eQADC SSI Timing
FCK falling-edge
FCK rising-edge
FCK
Rating
DDEH
= 1
SDO
SDS
FCK
÷
SDI
= 3.0–5.25 V, T
f
FCK
Table 27. EQADC SSI Timing Characteristics
)
MPC5553 Microcontroller Data Sheet, Rev. 3.0
1, 2
Figure 27. EQADC SSI Timing
A
= T
L
Symbol
t
t
t
t
t
t
SDO_LL
to T
SDS_LL
EQ_SU
EQ_HO
5
FCKHT
6
FCKLT
t
FCK
3
H
, and CL = 25 pF with SRC = 0b11. Maximum operating frequency
2
1st (MSB)
4
t
t
SYS_CLK
SYS_CLK
7
Minimum
1st (MSB) 2nd
–7.5
–7.5
22
2
1
8
− 6.5
− 6.5
2nd
Typical
—
—
—
—
—
—
—
25th
25th
9 × (t
8 × (t
26th
Maximum
SYS_CLK
SYS_CLK
Freescale Semiconductor
+7.5
+7.5
17
—
—
4
5
+ 6.5)
+ 6.5)
26th
t
SYS_CLK
Unit
ns
ns
ns
ns
ns
ns
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