M37702E6BFS Renesas Electronics America, M37702E6BFS Datasheet - Page 285
M37702E6BFS
Manufacturer Part Number
M37702E6BFS
Description
EPROM MCU/8BIT CMOS EMULATION CH
Manufacturer
Renesas Electronics America
Datasheet
1.M37702E6BFS.pdf
(524 pages)
Specifications of M37702E6BFS
Accessory Type
Emulator EPROM MCU
For Use With/related Products
7702
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
M37702E6BFS
Manufacturer:
MITSUBISHI/三菱
Quantity:
20 000
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Fig. 12.4.1 Judgment when accessing word data beginning from odd address with 2-bus cycle
not in use, the judgment is performed at every falling of . While the bus is in use, judgment is performed
at the falling of the last
address with 2-bus cycle, the judgment is performed only at the second bus cycle. (See Figure 12.4.1.)
called acceptance of Hold request.)
changes “H” to “L”. When 1 cycle of
and the external bus become floating state.
detected, the HLDA pin’s level changes “L” to “H” next rising of . When 1 cycle of
level of HLDA pin becomes “H”, the microcomputer terminates Hold state.
Note:
12.4.1 Operation description
Judgment timing of the input level of the HOLD pin depends on the state using the bus. While the bus is
When “L” level is detected at judgment of the input level, the microcomputer enters Hold state. (This is
When the Hold request is accepted,
In Hold state, the input level of the HOLD pin is judged at every falling of . Then, when “H” level is
Figures 12.4.2 to 12.4.4 show timing of acceptance of Hold request and termination of Hold state.
or executing the STP or WIT instruction. Accordingly, judgment of the input level of the HOLD pin
is not performed during Ready state.
has a same polarity and a same frequency as the clock
_____
_____
Judgment timing of input level to HOLD pin
CONNECTION WITH EXTERNAL DEVICES
in each bus cycle. Additionally, when accessing word data starting from an odd
has passed after the level of HLDA pin becomes “L”, pins R/W, BHE,
_____
CPU
7702/7703 Group User’s Manual
Reading
_____
Clock
Writing
stops next rising of
ALE
E
Accessing word data with 2-bus cycle.
(Example of no Wait)
1
A
A
No judge
W
A
A
Judge
. At the same time, the HLDA pin’s level
1
. However,
W
_____
stops by the Ready request,
12.4 Hold function
has passed after the
_____
_____
__
12–17
___
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