ISL6140/41EVAL1 Intersil, ISL6140/41EVAL1 Datasheet - Page 5

• Manufacturer Part Number: ISL6140/41EVAL1
• Description: EVALUATION BOARD NEG ISL6140/41
• Manufacturer: Intersil
• Type: Hot-Swap Controllerr

Specifications of ISL6140/41EVAL1

• Contents: Fully Assembled Evaluation Board
• For Use With/related Products: ISL6140, 6141
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

provides a current path between the PWRGD pin back to the
VEE pin, when the FET is off; this may not be desirable in
the system (referencing the LED to the DRAIN pin doesn’t
work, since under most faults, when the FET turns off, the
DRAIN will then be floating.
Since the ISL6140/41 PWRGD output is an open-drain, pull-
down device, an LED connected to the positive supply is
another option. But since the LED will be on during normal
operation, and off during a fault, a green “OK” LED is
suggested. See “Optional Components” section for more
details.
Required Components
B channels; See Fig. 4 and 7)
U1 is the ISL6140 (L) or ISL6141 (L) Intersil hot plug
controller IC. The ISL6141 is an enhanced version of the
ISL6140 and is pin for pin compatible. The functional
differences are summarized on page 1.The ISL6150 and
ISL6151 function and perform the same as the ISL6140 and
ISL6141 respectively, with the exception of their power good
outputs which are active high.
R4, R5, R6, are the resistors that divide the input power
supply voltage down to the Over-Voltage (OV) and Under-
voltage (UV) trip points. The top of the resistor divider is
connected to the short-pin GND.
R3, C2, R2, C1 control the inrush current, prevent
momentary turn-on during power-up, and keep the gate pin
from oscillating. See ISL6140/41 data sheets for more
details.
R1 is the Over-Current sense resistor. I
Q1 is the FET that switches the voltage from the input BUS
to the LOAD. It uses a D2PAK package.
R8, R9, D4, D5 create the red LED “FAULT” indication for
the ISL6140/41 (L version). R8 sets the LED current; R9 is
just a zero ohm placeholder; D5 is the LED, and D4 is a 3V
zener. Note that when the PWRGD open-drain pull-down
output turns on (Power is Good), the fault LED is off. When
the output turns off, the fault LED will turn on; the voltage
would rise to a high value, but the zener and LED will clamp
it to approximately 4.5V.
R4
R5
R6
GND
-48V IN
UV
OV
FIGURE 4. TYPICAL APPLICATION
VEE
R1
SENSE
ISL6140/41
VDD
C1
GATE
5
Q1
R2
(Same for both A and
R3
OC
PWRGD
C2
DRAIN
= 50 mV / R1.
-48V OUT
GND
RL
(LOAD)
CL
R1 = 0.02Ω (1%)
R2 = 10Ω (5%)
R3 = 18kΩ (5%)
R4 = 562kΩ (1%)
R5 = 9.09kΩ (1%)
R6 = 10kΩ (1%)
Optional Components
channels; See Fig. 7)
R10 and C4 make an RC filter for the VDD pin. It is used to
isolate some kinds of system supply noise from the IC. For
example, it may help filter out glitches that could trigger OV
or UV (which shut off the FET) if near their trip points.
D1 is a voltage suppressor, which can help protect the board
components from transient voltages that exceed the normal
operating range allowed (absolute maximum is 100V).
D2 and D3 may be used to block inductive transients that
might pull the drain pin negative with respect to the VEE pin.
The ISL6140/41 (L version) uses one diode (D2); the
ISL6150/51 (H version) uses both diodes. The diodes have a
second effect of offsetting the drain trip points for the
PWRGD/ PWRGD output. The default board has one of the
diodes shorted out with zero ohms; that should be removed
before adding one or two diodes.
R7 and C3 make an RC time constant to lengthen the time
allowed in the Over-Current condition for the ISL6140,
before shutting down. Without them, any pulse longer than
the 2–4 usec spec would latch off the output. If noise pulses
wider than that are expected (and won’t cause other
damage), then set the filter to a time longer than those
pulses. Note, however, that the FET must be able to safely
handle the current and power dissipation for that longer time
period. The default boards are shipped with R7 = zero
ohms.The ISL6141/51 does not require these components,
as the device has a fixed 600uS time-out and programmable
current limiting.
Q2 and Q3 are alternate package options for Q1 FETs. Q2 is
an 8-pin SOIC, using a standard pinout (S=1, 2, 3, G=4,
D=5-8). Q3 is an SOT-223 package. Since all three pins of
all three packages are wired in parallel, with no jumpers, it is
recommended that only one of the 3 be populated at any
given time.
R1_alt is a 0.020 Ω sense resistor; if used instead of R1 (un-
solder R1, and solder in R1_alt) it will produce an Over-
Current trip point of (50mV /0.020Ω) = 2.5 Amps. CAUTION:
The load resistors supplied with the LOAD board combined
only give about 0.25Amps for each channel; an additional
TABLE 1. NEEDS A DESCRIPTION
C1 = 150nF (25V)
C2 = 3.3nF (100V)
Q1 = IRF530 (100V, 17A, 0.11Ω)
CL = 100µF (100V)
RL = equivalent resistance of the
Load
(Same for both A and B