HS7751RKCI02H Renesas Electronics America, HS7751RKCI02H Datasheet - Page 248

• Manufacturer Part Number: HS7751RKCI02H
• Description: ON CHIP DEBUG EMULATOR W/TRACE
• Manufacturer: Renesas Electronics America

Specifications of HS7751RKCI02H

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Table 6.13 Performance Count Conditions (cont)
Event
Pipeline freeze cycle due
to branch instruction or
exception
220
Counting method
One of the following methods can be specified by each of measurement channels 1 and 2.
1. Counted by the CPU operating clock
2. Counted by the ratio of the CPU operating clock to the bus clock
When the above method 1 is specified, one CPU operating clock cycle is counted as
one. When method 2 is specified, the count is incremented by 3, 4, 6, 8, 12, or 24,
according to the clock frequency ratio (ratio of the CPU clock to the bus clock). In this
case, the execution time can be calculated by the following expression:
When the ratio of the CPU clock to the bus clock is changed in the user program, it is
recommended to select method 2, above, to count the number of cycles.
The following shows examples to measure the performance of the user program by the
performance measurement function.
1. Measuring cache hit ratio
Specify measurement channel 1 to count the cache misses (for data read and write)
and specify measurement channel 2 to count operand accesses (read and write) to the
cacheable area while the cache is enabled. Specify, with both the channels, the
measurement from the start to the end of user program execution.
With the above command settings, the cache miss count and the access count to the
cacheable area can be measured, and the cache hit ratio in the executed user program
can be obtained.
T = C x B / 24
Count Condition
Counts only one cycle at branch instruction
execution except when the delay slot instruction is
executed with one-cycle delay. One instruction is
executed in one cycle, which is similar to the
branch count. When the instruction in the branch
destination does not exist in the instruction cache,
the delay after the second cycle is counted by the
ECF. In the PFB, all branch instructions can be
counted.
(T: Execution time; B: Time of one bus clock cycle; C: Count)
Target Mode
PFB