M5271EVB Freescale Semiconductor, M5271EVB Datasheet

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... In addition, the MCF5271 family features an enhanced multiply accumulate unit (eMAC), large on-chip memory (64 Kbytes SRAM, 8 Kbytes configurable cache), and a 32-bit SDR SDRAM memory controller. © Freescale Semiconductor, Inc., 2009. All rights reserved. ® family of reduced 1 MCF5271 Family Configurations . . . . . . . . . . . . . . . . . . . 2 2 Block Diagram ...

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... The superset device in the MCF5271 family comes in a 196 mold array plastic ball grid array (MAPBGA) package. Figure 1 shows a top-level block diagram of the MCF5271. MCF5271 Integrated Microprocessor Hardware Specification, Rev Table 1. MCF5271 Family Configurations Module MCF5270 — 160 QFP, 196 MAPBGA MCF5271 x 150 MHz 144 8 Kbytes 64 Kbytes 160 QFP, 196 MAPBGA Freescale Semiconductor ...

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... PADI) CONTROLLER (FEC) (To/From PADI DMA (To/From PADI) DREQ[2:0] DACK[2:0] JTAG_EN JTAG TAP Watchdog Timer SKHA RNGA MDHA Cryptography Modules MCF5271 Integrated Microprocessor Hardware Specification, Rev. 4 Freescale Semiconductor (To/From SRAM backdoor) INTC0 INTC1 Arbiter UART UART UART DTIM DTIM DTIM DTIM 1 2 ...

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... O — — O Mode Selection — — I — — I External Memory Interface and Ports CS[6:4] — O 126, 125, 124 Numbers,” for package diagrams. MCF5270 MCF5271 196 MAPBGA 83 N13 82 P13 86 M14 85 N14 89 K14 20,21 G5,H5 79 K10 B11, C11, D11 Freescale Semiconductor ...

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... CS[3:2] PCS[3:2] CS1 PCS1 CS0 — SD_WE PSDRAM5 SD_SCAS PSDRAM4 SD_SRAS PSDRAM3 SD_CKE PSDRAM2 SD_CS[1:0] PSDRAM[1:0] MCF5271 Integrated Microprocessor Hardware Specification, Rev. 4 Freescale Semiconductor MCF5270 1 Alternate 1 Alternate 2 Dir. MCF5271 160 QFP — — O 123:115, 112:106, 102:98 — — O 22:30, 33:39 — ...

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... SD_CKE — O — — O I2C_SCL — O I2C_SDA — I — — O MCF5270 MCF5271 196 MAPBGA N7, M7, L7, P8, N8 — 151 D4 150 5:2 D3, C1, C2, B1 159 B2 158 A2 157 C3 156 B3 A3, A4, C4, B4 — J12 — J11 — — 139 B7 146 A6 147 C5 148 B5 149 A5 Freescale Semiconductor ...

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... PTIMER0 DSCLK — PSTCLK — BKPT — DSI — DSO — JTAG_EN — DDATA[3:0] — PST[3:0] — MCF5271 Integrated Microprocessor Hardware Specification, Rev. 4 Freescale Semiconductor MCF5270 1 Alternate 1 Alternate 2 Dir. MCF5271 160 QFP UARTs — — O — — I U2CTS — I U2RTS — ...

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... I 16, 53, 103 MCF5270 MCF5271 196 MAPBGA 19 F5 — 87 M13 84 L14 E5, E7, E10, F7, F9, G6, G8, H7, H8, H9, J6, J8, 145 J10, K5, K6, K8 A1, A14, E6, E9, F6, F8, F10, G7, G9, H6, J5, J7, J9, K7, P1, P14 D6, F11, G4, L4 Freescale Semiconductor ...

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... powered down first, then sense circuits in the I/O pads cause all output drivers high DD impedance state. There is no limit on how long after V down. V should not lag MCF5271 Integrated Microprocessor Hardware Specification, Rev. 4 Freescale Semiconductor (OV ), PLL Supplies Stable then the sense circuits in the I/O pads cause all pad output drivers ...

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... Tie XTAL to ground when an external oscillator is clocking the device. 5.7 Interface Recommendations 5.7.1 SDRAM Controller 5.7.1.1 SDRAM Controller Signals in Synchronous Mode Table 3 shows the behavior of SDRAM signals in synchronous mode. MCF5271 Integrated Microprocessor Hardware Specification, Rev Section 7, “Electrical Characteristics.” Freescale Semiconductor ...

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... FEC module supports 18 signals. These are shown in Transmit clock Transmit enable Transmit data Transmit error Collision Carrier sense Receive clock Receive enable Receive data MCF5271 Integrated Microprocessor Hardware Specification, Rev. 4 Freescale Semiconductor Description Table 4. MII Mode Signal Description MCF5271 Pin ETXCLK ETXEN ETXD[3:0] ETXER ECOL ECRS ...

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... Unused output, ignore Unused, configure as PB[10:8] Unused, configure as PB15 Input after reset, connect to ground Refer to the M5271EVB evaluation board user’s manual for an example of how to connect an external PHY. Schematics for this board are accessible at the MCF5271 site by navigating to: http://www.freescale.com/coldfire. 5.7.3 BDM Use the BDM interface as shown in the M5271EVB evaluation board user’ ...

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... D10 L VDD_2 D15 D13 D14 D12 VSS D11 Figure 3. MCF5270/71CVMxxx Pinout (196 MAPBGA) MCF5271 Integrated Microprocessor Hardware Specification, Rev. 4 Freescale Semiconductor QSPI_ QSPI_CS0 U2RXD U2TXD DOUT QSPI_DIN BS3 QSPI_CS1 U1CTS QSCK BS2 BS0 RTS1 Core EMDIO BS1 U1RXD1 VDD_4 VDD VSS ...

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... Parallelism measurement shall exclude any effect of mark on top surface of package. Millimeters DIM Min Max A 1.25 1.60 A1 0.27 0.47 A2 1.16 REF b 0.45 0.55 D 15.00 BSC E 15.00 BSC e 1.00 BSC S 0.50 BSC 196X Detail K Rotated 90° Clockwise Freescale Semiconductor ...

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... DATA22 34 DATA21 35 DATA20 36 DATA19 37 DATA18 38 DATA17 39 DATA16 40 VSS Figure 5. MCF5270/71CABxxx Pinout (160 QFP) MCF5271 Integrated Microprocessor Hardware Specification, Rev. 4 Freescale Semiconductor Mechanicals/Pinouts and Part Numbers MCF5271 120 A17 119 A16 118 A15 117 A14 116 A13 115 A12 114 O-VDD 113 ...

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... R 0.13 0.30 0.005 0.012 S 31.00 31.40 1.220 1.236 0.13 — 0.005 — T ° ° — 0 — V 31.00 31.40 1.220 1.236 W 0.4 — 0.016 — X 1.60 REF 0.063 REF Y 1.33 REF 0.052 REF Z 1.33 REF 0.052 REF Freescale Semiconductor ° ° 7 ...

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... Ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Continued operation at these levels may affect device reliability or cause permanent damage to the device. MCF5271 Integrated Microprocessor Hardware Specification, Rev. 4 Freescale Semiconductor Table 6. Orderable Part Numbers Package 160 QFP 160 QFP ...

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... J ( × Θ ( JMA and range during instantaneous DD > greater in DD range during DD 196 Symbol 160QFP MAPBGA θ 1,2 1 JMA θ 1,2 1 JMA θ θ Ψ 1,5 1 104 105 j Freescale Semiconductor Unit ° ° ° ° ° ...

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... Output Low Voltage (All input/output and all output pins 5.0mA OL Weak Internal Pull Up Device Current, tested Input Capacitance All input-only pins All input/output (three-state) pins MCF5271 Integrated Microprocessor Hardware Specification, Rev. 4 Freescale Semiconductor < P and can be ignored. An approximate relationship between P INT ÷ ...

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... TBD — –1.0 1.0 – and could DD load will shunt current greater than maximum 1 Min. Max. Unit Value Value MHz 150 MHz 0 75 MHz ÷ MHz ref 100 1000 kHz 10.25 15.25 MHz — Freescale Semiconductor Unit μ ...

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... Modulation percentage applies over an interval of 10μs, or equivalently the modulation rate is 100KHz. 14 Modulation rate selected must not result in f Modulation range determined by hardware design. 15 RFD sys/2 ico * MCF5271 Integrated Microprocessor Hardware Specification, Rev. 4 Freescale Semiconductor Symbol 5 t lpll 5, 6,8 t lplk 9 t skew ...

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... MCF5271 Integrated Microprocessor Hardware Specification, Rev NOTE 1 Characteristic Control Inputs Data Inputs Symbol Min Max Unit MHz sys/2 t — 1/75 ns cyc t 9 — ns CVCH t 9 — ns BKVCH t 0 — ns CHCII t 0 — ns BKNCH t 4 — ns DIVCH t 0 — ns CHDII Freescale Semiconductor ...

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... CLKOUT high to chip selects valid B6b CLKOUT high to byte enables (BS[3:0]) valid B6c CLKOUT high to output enable (OE) valid B7 CLKOUT high to control output (BS[3:0], OE) invalid B7a CLKOUT high to chip selects invalid MCF5271 Integrated Microprocessor Hardware Specification, Rev. 4 Freescale Semiconductor Figure 7. CLKOUT(75MHz) T SETUP Invalid 1.5V Valid ...

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... BS transitions after the falling edge of CLKOUT transitions after the falling edge of CLKOUT. MCF5271 Integrated Microprocessor Hardware Specification, Rev Symbol Address and Attribute Outputs t CHAV t CHAI Data Outputs t CHDOV t CHDOI t CHDOZ Min Max Unit — 1.5 — ns — 1.5 — ns — Freescale Semiconductor ...

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... Read/write bus timings listed in S0 CLKOUT B6a CSn B8 A[23:0] TSIZ[1: TIP B8 B6c OE (H) R/W B6b BS[3:0] D[31:0] (H) TA TEA (H) Figure 8. Read/Write (Internally Terminated) SRAM Bus Timing MCF5271 Integrated Microprocessor Hardware Specification, Rev. 4 Freescale Semiconductor Table 12 are shown in Figure B7a B6b Electrical Characteristics Figure 9, and Figure 10 ...

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... Figure 9 shows a bus cycle terminated by TA showing timings listed in CLKOUT B6a CSn B8 A[23:0] TSIZ[1: TIP B6c OE (H) R/W B6b BS[3:0] D[31:0] TA TEA (H) Figure 9. SRAM Read Bus Cycle Terminated by TA MCF5271 Integrated Microprocessor Hardware Specification, Rev B7a B2a B1a Table 12 Freescale Semiconductor ...

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... SRAM bus cycle terminated by TEA showing timings listed in CLKOUT B6a CSn B8 A[23:0] TSIZ[1: TIP B6c OE (H) R/W B6b BS[3:0] D[31:0] TA (H) TEA Figure 10. SRAM Read Bus Cycle Terminated by TEA MCF5271 Integrated Microprocessor Hardware Specification, Rev. 4 Freescale Semiconductor B7a B1a B2a Electrical Characteristics Table 12 ...

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... D3 Column NOP READ NOP Figure 11. SDRAM Read Cycle Table 13. SDRAM Timing Characteristic PALL Symbol Min Max t — 9 CHDAV t — 9 CHDCV t 1.5 — CHDAI t 1.5 — CHDCI t 4 — DDVCH t 1.5 — CHDDI t — 9 CHDDVW t 1.5 — CHDDIW Freescale Semiconductor Unit ...

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... NUM G1 CLKOUT High to GPIO Output Valid G2 CLKOUT High to GPIO Output Invalid G3 GPIO Input Valid to CLKOUT High G4 CLKOUT High to GPIO Input Invalid 1 GPIO pins include: INT, UART, Timer, DREQn and DACKn pins. MCF5271 Integrated Microprocessor Hardware Specification, Rev. 4 Freescale Semiconductor NOP WRITE NOP Figure 12 ...

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... Figure 13. GPIO Timing (V = 2 Characteristic levels unless otherwise noted Symbol Min Max t 9 — RVCH t 1.5 — CHRI t 5 — RIVT t — 10 CHROV t 0 — ROVCV t 20 — COS t 0 — COH t — 1 ROICZ Freescale Semiconductor Unit CYC CYC ns t CYC R8 ...

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... I2C_SCL or I2C_SDA take to reach a high level depends on external signal capacitance and pull-up resistor values. 3 Specified at a nominal 50-pF load. Figure 15 shows timing for the values in MCF5271 Integrated Microprocessor Hardware Specification, Rev. 4 Freescale Semiconductor 2 C input timing parameters shown in Characteristic = 0 2 ...

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... ERXCLK (input) ERXD[3:0] (inputs) ERXDV ERXER Figure 16. MII Receive Signal Timing Diagram MCF5271 Integrated Microprocessor Hardware Specification, Rev Figure 15 Input/Output Timings Table 18. MII Receive Signal Timing Characteristic Table 18 Min Max Unit 5 — — ns 35% 65% ERXCLK period 35% 65% ERXCLK period M4 Freescale Semiconductor ...

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... MII asynchronous inputs signal timing. Num M9 ECRS, ECOL minimum pulse width Figure 18 shows MII asynchronous input timings listed in ECRS, ECOL MCF5271 Integrated Microprocessor Hardware Specification, Rev. 4 Freescale Semiconductor Table 19. MII Transmit Signal Timing Characteristic Table 19 Table 20. MII Async Inputs Signal Timing ...

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... EMDC (output) EMDIO (output) EMDIO (input) Figure 19. MII Serial Management Channel Timing Diagram MCF5271 Integrated Microprocessor Hardware Specification, Rev Characteristic Table M14 M15 M10 M11 M12 M13 Min Max Unit 0 — ns — — — ns 40% 60% MDC period 40% 60% MDC period 21. Freescale Semiconductor ...

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... QSPI_DIN to QSPI_CLK (Input setup) QS5 QSPI_DIN to QSPI_CLK (Input hold) The values in Table 23 correspond to QS1 QSPI_CS[1:0] QSPI_CLK QSPI_DOUT QS3 QSPI_DIN MCF5271 Integrated Microprocessor Hardware Specification, Rev. 4 Freescale Semiconductor Characteristic Characteristic Figure 20. QS2 Figure 20. QSPI Timing Electrical Characteristics 0–66 MHz Unit Min Max 3 — ...

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... Figure 21. Test Clock Input Timing Symbol Min Max Unit f DC 1/4 f JCYC sys — t JCYC CYC t 26 — ns JCW JCRF t 4 — ns BSDST t 26 — ns BSDHT BSDV BSDZ t 4 — ns TAPBST t 10 — ns TAPBHT TDODV TDODZ t 100 — ns TRSTAT t 10 — ns TRSTST J3 Freescale Semiconductor ...

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... Data Outputs Data Outputs Data Outputs TCLK V IL TDI TMS TDO TDO TDO TCLK TRST MCF5271 Integrated Microprocessor Hardware Specification, Rev. 4 Freescale Semiconductor Figure 22. Boundary Scan (JTAG) Timing J9 Input Data Valid J11 J12 J11 Figure 23. Test Access Port Timing J14 J13 Figure 24 ...

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... MCF5271 Integrated Microprocessor Hardware Specification, Rev Table 25. Debug AC Timing Specification Characteristic Table 25. DE0 DE1 Figure 25. Real-Time Trace AC Timing Table Figure 26. 150 MHz Units Min Max — 0.5 t cyc 4 — ns 1.5 — — t cyc 1 — t cyc 4 — t cyc 4 — DE2 25. Freescale Semiconductor ...

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... DSO 8 Documentation Documentation regarding the MCF5271 and their development support tools is available from a local Freescale distributor, a Freescale semiconductor sales office, the Freescale Literature Distribution Center, or through the Freescale web address at http://www.freescale.com/coldfire. 9 Document Revision History The below table provides a revision history for this document. ...

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... Section 7.10.2, “MII Transmit Signal Timing ETXCLK),” as this feature is not supported on this device. to match rest of document. Sequence” first bullet, changed “Use 1 µs” to “Use 1 ms”. Figure 11. Table 6 Cautions.” 4. Cautions” changed PLLV to DD Cautions” Changed V DDPLL Freescale Semiconductor ...

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... MCF5271 Integrated Microprocessor Hardware Specification, Rev. 4 Freescale Semiconductor Document Revision History 41 ...

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... Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer ...