C8051F000-TB Silicon Laboratories Inc, C8051F000-TB Datasheet - Page 150
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C8051F000-TB
Manufacturer Part Number
C8051F000-TB
Description
BOARD PROTOTYPING W/C8051F000
Manufacturer
Silicon Laboratories Inc
Specifications of C8051F000-TB
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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Bit7:
Bit6:
Bit5:
Bit4:
Bit3:
Bit2:
Bit1:
Bit0:
R/W
TF2
Bit7
TF2: Timer 2 Overflow Flag.
Set by hardware when Timer 2 overflows from 0xFFFF to 0x0000 or reload value. When
the Timer 2 interrupt is enabled, setting this bit causes the CPU to vector to the Timer 2
interrupt service routine. This bit is not automatically cleared by hardware and must be
cleared by software. TF2 will not be set when RCLK and/or TCLK are logic 1.
Set by hardware when either a capture or reload is caused by a high-to-low transition on
the T2EX input pin and EXEN2 is logic 1. When the Timer 2 interrupt is enabled, setting
this bit causes the CPU to vector to the Timer 2 Interrupt service routine. This bit is not
automatically cleared by hardware and must be cleared by software.
Selects which timer is used for the UART’s receive clock in modes 1 or 3.
0: Timer 1 overflows used for receive clock.
1: Timer 2 overflows used for receive clock.
Selects which timer is used for the UART’s transmit clock in modes 1 or 3.
0: Timer 1 overflows used for transmit clock.
1: Timer 2 overflows used for transmit clock.
Enables high-to-low transitions on T2EX to trigger captures or reloads when Timer 2 is not
operating in Baud Rate Generator mode.
0: High-to-low transitions on T2EX ignored.
1: High-to-low transitions on T2EX cause a capture or reload.
TR2: Timer 2 Run Control.
This bit enables/disables Timer 2.
0: Timer 2 disabled.
1: Timer 2 enabled.
C/T2: Counter/Timer Select.
0: Timer Function: Timer 2 incremented by clock defined by T2M (CKCON.5).
1: Counter Function: Timer 2 incremented by high-to-low transitions on external input pin
(T2).
CP/RL2: Capture/Reload Select.
This bit selects whether Timer 2 functions in capture or auto-reload mode. EXEN2 must
be logic 1 for high-to-low transitions on T2EX to be recognized and used to trigger
captures or reloads. If RCLK or TCLK is set, this bit is ignored and Timer 2 will function
in auto-reload mode.
0: Auto-reload on Timer 2 overflow or high-to-low transition at T2EX (EXEN2 = 1).
1: Capture on high-to-low transition at T2EX (EXEN2 = 1).
EXF2: Timer 2 External Flag.
RCLK: Receive Clock Flag.
TCLK: Transmit Clock Flag.
EXEN2: Timer 2 External Enable.
EXF2
R/W
Bit6
Figure 19.14. T2CON: Timer 2 Control Register
RCLK
R/W
Bit5
TCLK
R/W
Bit4
Rev. 1.7
EXEN2
R/W
Bit3
TR2
R/W
Bit2
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
C/T2
R/W
Bit1
(bit addressable)
CP/RL2
R/W
Bit0
0xC8
SFR Address:
Reset Value
00000000
150
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