DSP56303EVM Freescale Semiconductor, DSP56303EVM Datasheet

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Technical Data DSP56303/D Rev. 7, 1/2002 24-Bit Digital Signal Processor Triple Timer The is DSP56303 intended for use in Generation telecommunication Six-Channel DMA Unit applications, such as multi-line voice/data/ Bootstrap fax processing, video ROM conferencing, audio applications, control, Internal and ...

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Table of Contents DSP56303 Features............................................................................................................................................ iii Target Applications ............................................................................................................................................ iv Product Documentation...................................................................................................................................... iv Chapter 1 Signal/ Connection Descriptions 1.1 Signal Groupings.............................................................................................................................................. 1-1 1.2 Power................................................................................................................................................................ 1-3 1.3 Ground.............................................................................................................................................................. 1-3 1.4 Clock ................................................................................................................................................................ 1-4 1.5 PLL................................................................................................................................................................... 1-4 1.6 External Memory Expansion Port ...

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DSP56303 Features High-Performance DSP56300 Core • 100 million instructions per second (MIPS) with a 100 MHz clock at 3.3 V nominal • Object code compatible with the DSP56000 core with highly parallel instruction set • Data Arithmetic Logic Unit (Data ...

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Off-Chip Memory Expansion • Data memory expansion to two 256 K address lines • Program memory expansion to one 256 K address lines • External memory expansion port • Chip Select Logic for glueless interface to static random access memory ...

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Chapter 1 Signal/ Connection Descriptions 1.1 Signal Groupings The DSP56303 input and output signals are organized into functional groups as shown in Table 1-1. Figure 1-1 diagrams the DSP56303 signals by functional group. The remainder of this chapter describes the ...

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Signal Groupings V CCP V CCQ V CCA V CCD V CCC V CCH V CCS GND P GND P1 GND Q GND A GND D GND C GND H GND S EXTAL XTAL CLKOUT PCAP After During Reset Reset ...

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Power Power Name V CCP V CCQ V CCA V CCD V CCC V CCH V CCS Note: The user must provide adequate external decoupling capacitors for all power connections. 1.3 Ground Ground Name GND P GND P1 2 ...

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Clock 1.4 Clock Signal Name EXTAL XTAL 1.5 PLL Signal Name CLKOUT PCAP PINIT NMI 1-4 Table 1-4. Clock Signals State Type During Reset Input Input External Clock/Crystal Input—Interfaces the internal crystal oscillator input to an external crystal or an ...

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External Memory Expansion Port (Port A) Note: When the DSP56303 enters a low-power standby mode (stop or wait), it releases bus mastership and tri-states the relevant Port A signals: CAS 1.6.1 External Address Bus Signal Name A[0–17] 1.6.2 External ...

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External Memory Expansion Port (Port A) 1.6.3 External Bus Control Signal Name AA[0–3] RAS[0– 1-6 Table 1-8. External Bus Control Signals State During Type Reset, Stop, or Wait Output Tri-stated Address Attribute—When defined as AA, these ...

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Table 1-8. External Bus Control Signals (Continued) State During Signal Type Reset, Stop, or Name Wait BG Input Ignored Input BB Input/ Ignored Input Output CAS Output Tri-stated BCLK Output Tri-stated BCLK Output Tri-stated External Memory Expansion Port (Port A) ...

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Interrupt and Mode Control 1.7 Interrupt and Mode Control The interrupt and mode control signals select the chip operating mode as it comes out of hardware reset. After RESET is deasserted, these inputs are hardware interrupt request lines. Signal Name ...

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Host Interface (HI08) The HI08 provides a fast, 8-bit, parallel data port that connects directly to the host bus. The HI08 supports a variety of standard buses and connects directly to a number of industry-standard microcomputers, microprocessors, DSPs, and ...

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Host Interface (HI08) Signal Name HA0 HAS/HAS PB8 HA1 HA8 PB9 HA2 HA9 PB10 HCS/HCS HA10 PB13 1-10 Table 1-11. Host Interface (Continued) State During Type 1,2 Reset Input Ignored Input Host Address Input 0—When the HI08 is programmed to ...

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Table 1-11. Host Interface (Continued) State During Signal Name Type Reset HRW Input Ignored Input HRD/HRD Input PB11 Input or Output HDS/HDS Input Ignored Input HWR/HWR Input PB12 Input or Output HREQ/HREQ Output Ignored Input HTRQ/HTRQ Output PB14 Input or ...

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Host Interface (HI08) Signal Name HACK/HACK HRRQ/HRRQ PB15 Notes: 1-12 Table 1-11. Host Interface (Continued) State During Type 1,2 Reset Input Ignored Input Host Acknowledge—When the HI08 is programmed to interface with a single host request host bus and the ...

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Enhanced Synchronous Serial Interface 0 (ESSI0) Two synchronous serial interfaces (ESSI0 and ESSI1) provide a full-duplex serial port for serial communication with a variety of serial devices, including one or more industry-standard codecs, other DSPs, microprocessors, and peripherals that ...

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Enhanced Synchronous Serial Interface 1 (ESSI1) Signal Name SRD0 PC4 STD0 PC5 Notes: 1.10 Enhanced Synchronous Serial Interface 1 (ESSI1) Signal Name SC10 PD0 SC11 PD1 1-14 Table 1-12. Enhanced Synchronous Serial Interface 0 (Continued) State During Type 1,2 Reset ...

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Table 1-13. Enhanced Serial Synchronous Interface 1 (Continued) State During Signal Name Type Reset SC12 Input/Output Ignored Input PD2 Input or Output SCK1 Input/Output Ignored Input PD3 Input or Output SRD1 Input Ignored Input PD4 Input or Output STD1 Output ...

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Serial Communication Interface (SCI) 1.11 Serial Communication Interface (SCI) The SCI provides a full duplex port for serial communication with other DSPs, microprocessors, or peripherals such as modems. Signal Name RXD PE0 TXD PE1 SCLK PE2 Notes: 1-16 Table 1-14. ...

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Timers The DSP56303 has three identical and independent timers. Each timer can use internal or external clocking and can either interrupt the DSP56303 after a specified number of events (clocks) or signal an external device after counting a specific ...

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JTAG and OnCE Interface 1.13 JTAG and OnCE Interface The DSP56300 family and in particular the DSP56303 support circuit-board test strategies based on the IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture, the industry standard developed under the ...

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Chapter 2 Specifications 2.1 Introduction The DSP56303 is fabricated in high-density CMOS with Transistor-Transistor Logic (TTL) compatible inputs and outputs. 2.2 Maximum Ratings Note: In the calculation of timing requirements, adding a maximum value of one specification to a minimum ...

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Absolute Maximum Ratings 2.3 Absolute Maximum Ratings Supply Voltage All input voltages excluding “5 V tolerant” inputs All “5 V tolerant” input voltages Current drain per pin excluding V Operating temperature range Storage temperature Notes: 2.4 Thermal Characteristics Junction-to-ambient thermal ...

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DC Electrical Characteristics Supply voltage Input high voltage • D[0–23], BG, BB • MOD JTAG/ESSI/SCI/Timer/HI08 pins • EXTAL Input low voltage • D[0–23], BG, BB, TA, MOD • All JTAG/ESSI/SCI/Timer/HI08 pins • EXTAL Input leakage current High ...

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AC Electrical Characteristics 2.6 AC Electrical Characteristics The timing waveforms shown in the AC electrical characteristics section are tested with 0.3 V and a V shown in Note 6 of the previous table. AC timing specifications, which ...

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External Clock Operation The DSP56303 system clock is derived from the on-chip oscillator or is externally supplied. To use the on-chip oscillator, connect a crystal and associated resistor/capacitor components to EXTAL and XTAL; examples are shown in Figure 2-1 ...

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AC Electrical Characteristics No. 1 Frequency of EXTAL (EXTAL Pin Frequency) The rise and fall time of this external clock should maximum. 2 EXTAL input high • • 3 EXTAL input low • • 4 EXTAL cycle ...

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Reset, Stop, Mode Select, and Interrupt Timing Table 2-7. Reset, Stop, Mode Select, and Interrupt Timing No. Characteristics 8 Delay from RESET assertion to all pins at reset value 4 9 Required RESET duration • Power on, external clock ...

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AC Electrical Characteristics Table 2-7. Reset, Stop, Mode Select, and Interrupt Timing No. Characteristics 25 Delay from IRQA assertion to fetch of first instruction (when exiting 2, 3 Stop) • PLL is not active during Stop (PCTL Bit 17 = ...

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Table 2-7. Reset, Stop, Mode Select, and Interrupt Timing No. Characteristics Notes: 1. When fast interrupts are used and IRQA, IRQB, IRQC, and IRQD are defined as level-sensitive, timings 19 through 21 apply to prevent multiple interrupt service. To avoid ...

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AC Electrical Characteristics IRQA, IRQB, IRQC, IRQD, IRQA, IRQB, IRQC, IRQD, 2-10 CLKOUT 11 RESET A[0–17] Figure 2-4. Synchronous Reset Timing A[0–17 NMI a) First Interrupt Instruction Execution General Purpose I/O 18 NMI b) General-Purpose I/O Figure ...

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IRQA, IRQB, IRQC, IRQD, NMI IRQA, IRQB, IRQC, IRQD, NMI Figure 2-6. External Interrupt Timing (Negative Edge-Triggered) CLKOUT IRQA, IRQB, IRQC, IRQD, NMI A[0–17] Figure 2-7. Synchronous Interrupt from Wait State Timing RESET MODA, MODB, MODC, MODD, PINIT Figure 2-8. ...

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AC Electrical Characteristics IRQA, IRQB, IRQC, IRQD, 2-12 24 IRQA A[0–17] Figure 2-9. Recovery from Stop State Using IRQA IRQA A[0–17] Figure 2-10. Recovery from Stop State Using IRQA Interrupt Service A[0–17 First Interrupt Instruction Execution NMI ...

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External Memory Expansion Port (Port A) 2.6.5.1 SRAM Timing No. 100 Address valid and AA assertion pulse width 101 Address and AA valid to WR assertion 102 WR assertion pulse width 103 WR deassertion to address not valid 104 ...

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AC Electrical Characteristics No. 111 WR deassertion to data high impedance 112 Previous RD deassertion to data active (write) 113 RD deassertion time 114 WR deassertion time 115 Address valid to RD assertion 116 RD assertion pulse width 117 RD ...

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A[0–17] AA[0–3] 113 D[0–23] Note: Address lines A[0–17] hold their state after a read or write operation. AA[0–3] do not hold their state after a read or write operation. Figure 2-12. SRAM Read Access A[0–17] AA[0–3] 101 ...

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AC Electrical Characteristics 2.6.5.2 DRAM Timing The selection guides in Figure 2-14 and Figure 2-17 are for primary selection only. Final selection should be based on the timing in the following tables. For example, the selection guide suggests that four ...

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Table 2-9. DRAM Page Mode Timings, Three Wait States No. Characteristics 131 Page mode cycle time for two consecutive accesses of the same direction Page mode cycle time for mixed (read and write) accesses 132 CAS assertion to data valid ...

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AC Electrical Characteristics No. 131 Page mode cycle time for two consecutive accesses of the same direction Page mode cycle time for mixed (read and write) accesses 132 CAS assertion to data valid (read) 133 Column address valid to data ...

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RAS CAS 137 Column Row A[0–17] Address Add WR RD 155 D[0–23] Data Out Figure 2-15. DRAM Page Mode Write Accesses RAS CAS 137 Row Column A[0–17] Add Address WR RD D[0–23] Figure 2-16. DRAM Page Mode Read Accesses AC ...

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AC Electrical Characteristics Table 2-11. DRAM Out-of-Page and Refresh Timings, Eleven Wait States No. 157 Random read or write cycle time 158 RAS assertion to data valid (read) 159 CAS assertion to data valid (read) 160 Column address valid to ...

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Table 2-11. DRAM Out-of-Page and Refresh Timings, Eleven Wait States No. Characteristics 171 Row address valid to RAS assertion 172 RAS assertion to row address not valid 173 Column address valid to CAS assertion 174 CAS assertion to column address ...

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AC Electrical Characteristics Table 2-12. DRAM Out-of-Page and Refresh Timings, Fifteen Wait States No. 157 Random read or write cycle time 158 RAS assertion to data valid (read) 159 CAS assertion to data valid (read) 160 Column address valid to ...

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Table 2-12. DRAM Out-of-Page and Refresh Timings, Fifteen Wait States No. Characteristics Notes: 1. The number of wait states for an out-of-page access is specified in the DRAM Control Register. 2. The refresh period is specified in the DRAM Control ...

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AC Electrical Characteristics RAS CAS WR 2-24 162 RAS 169 170 CAS 171 Row Address A[0–17 D[0–23] Figure 2-19. DRAM Out-of-Page Write Access 162 190 170 177 Figure 2-20. DRAM Refresh Access 157 163 165 167 164 168 ...

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Synchronous Timings Table 2-13. External Bus Synchronous Timings No. Characteristics 198 CLKOUT high to address, and AA valid 199 CLKOUT high to address, and AA invalid 200 TA valid to CLKOUT high (set-up time) 201 CLKOUT high to TA ...

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AC Electrical Characteristics CLKOUT A[0–17] AA[0–3] D[0–23] D[0–23] Note: Address lines A[0–17] hold their state after a read or write operation. AA[0–3] do not hold their state after a read or write operation. CLKOUT A[0–17] AA[0–3] D[0–23] D[0–23] Note: Address ...

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Arbitration Timings Table 2-14. Arbitration Bus Timings No. Characteristics 212 CLKOUT high to BR assertion/deassertion 213 BG asserted/deasserted to CLKOUT high (setup) 214 CLKOUT high to BG deasserted/asserted (hold) 215 BB deassertion to CLKOUT high (input set-up) 216 CLKOUT ...

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AC Electrical Characteristics CLKOUT A[0–17] RD, WR AA[0–3] Note: Address lines A[0–17] hold their state after a read or write operation. AA[0–3] do not hold their state after a read or write operation. CLKOUT A[0–17] RD, WR AA[0–3] Note: Address ...

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CLKOUT 212 A[0–17] RD, WR AA[0–3] Note: Address lines A[0–17] hold their state after a read or write operation. AA[0–3] do not hold their state after a read or write operation. Figure 2-25. Bus Release Timings Case ...

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AC Electrical Characteristics 2.6.5.5 Asynchronous Bus Arbitration Timings No. 250 BB assertion window from BG input deassertion 251 Delay from BB assertion to BG assertion Notes: The asynchronous bus arbitration is enabled by internal synchronization circuits on These synchronization circuits ...

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Host Interface Timing No. 317 Read data strobe assertion width HACK assertion width 318 Read data strobe deassertion width HACK deassertion width 319 Read data strobe deassertion width reads HACK deassertion width after “Last Data Register” reads 320 Write ...

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AC Electrical Characteristics No. 338 Delay from read data strobe deassertion to host request assertion for “Last Data Register” read 339 Delay from write data strobe deassertion to host request assertion for “Last Data Register” write 340 Delay from data ...

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Figure 2-28. Read Timing Diagram, Non-Multiplexed Bus, Single Data Strobe Figure 2-29. Read Timing Diagram, Non-Multiplexed Bus, Double Data Strobe 2-33 ...

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AC Electrical Characteristics Figure 2-31. Write Timing Diagram, Non-Multiplexed Bus, Double Data Strobe 2-34 HA[2–0] HCS 336 HRW HDS H[7–0] HREQ (single host request) HTRQ (double host request) Figure 2-30. Write Timing Diagram, Non-Multiplexed Bus, Single Data Strobe HA[2–0] HCS ...

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HA[10–8] 322 HAS 336 HRW HDS 334 HAD[7–0] Address HREQ (single host request) HRRQ (double host request) Figure 2-32. Read Timing Diagram, Multiplexed Bus, Single Data Strobe HA[10–8] 322 HAS HRD 334 HAD[7–0] Address HREQ (single host request) HRRQ ...

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AC Electrical Characteristics 2-36 HA[10–8] 322 HAS 336 HRW HDS 334 335 HAD[7–0] Address HREQ (single host request) HTRQ (double host request) Figure 2-34. Write Timing Diagram, Multiplexed Bus, Single Data Strobe , HA[10–8] 322 HAS HWR 334 335 HAD[7–0] ...

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SCI Timing No. 400 Synchronous clock cycle 401 Clock low period 402 Clock high period 403 Output data setup to clock falling edge (internal clock) 404 Output data hold after clock rising edge (internal clock) 405 Input data setup ...

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AC Electrical Characteristics 2-38 SCLK (Output) 403 Data Valid TXD Data RXD Valid SCLK (Input) 407 TXD 409 RXD b) External Clock Figure 2-36. SCI Synchronous Mode Timing 1X SCLK (Output) TXD Figure 2-37. SCI Asynchronous Mode Timing 400 402 ...

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ESSI0/ESSI1 Timing No. 430 Clock cycle 431 Clock high period • • 432 Clock low period • • 433 RXC rising edge to FSR out (bit-length) high 434 RXC rising edge to FSR out (bit-length) low 435 RXC rising ...

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AC Electrical Characteristics No. 450 TXC rising edge to FST out (word-length) high 451 TXC rising edge to FST out (word-length) low 452 TXC rising edge to data out enable from high impedance 453 TXC rising edge to Transmitter #0 ...

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TXC (Input/ Output) 446 447 FST (Bit) Out 450 FST (Word) Out 454 452 Data Out 459 Transmitter #0 Drive Enable 457 FST (Bit) In 458 FST (Word) In Flags Out Note: In Network mode, output flag transitions ...

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AC Electrical Characteristics 2-42 430 431 RXC 432 (Input/ Output) 433 434 FSR (Bit) Out 437 FSR (Word) Out 439 Data In 443 441 FSR (Bit) In 442 FSR (Word) In 444 Flags In Figure 2-39. ESSI Receiver Timing 438 ...

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Timer Timing No. 480 481 482 483 484 485 Notes: TIO Table 2-19. Timer Timing Characteristics TIO Low TIO High Timer set-up time from TIO (Input) assertion to CLKOUT rising edge Synchronous timer delay time from CLKOUT rising edge ...

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AC Electrical Characteristics 2.6.10 GPIO Timing No. 490 CLKOUT edge to GPIO out valid (GPIO out delay time) 491 CLKOUT edge to GPIO out not valid (GPIO out hold time) 492 GPIO In valid to CLKOUT edge (GPIO in set-up ...

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JTAG Timing No. 500 501 502 503 504 505 506 507 508 509 510 511 512 513 Notes: TCK (Input) Table 2-21. JTAG Timing Characteristics TCK frequency of operation TCK cycle time in Crystal mode TCK clock pulse width ...

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AC Electrical Characteristics TCK (Input) Data Inputs Data Outputs Data Outputs Data Outputs TCK (Input) TDI TMS (Input) TDO (Output) TDO (Output) TDO (Output) TCK (Input) TRST (Input) 2- 506 507 506 Figure 2-45. Boundary Scan (JTAG) Timing ...

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OnCE Module TimIng No. 500 TCK frequency of operation 514 DE assertion time in order to enter Debug mode 515 Response time when DSP56303 is executing NOP instructions from internal memory 516 Debug acknowledge assertion time Note: DE Table ...

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AC Electrical Characteristics 2-48 ...

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Chapter 3 Packaging 3.1 Pin-Out and Package Information This section includes diagrams of the signals described in The DSP56303 is available in two package types: • 144-pin Thin Quad Flat Pack (TQFP) • 196-pin Molded Array Process-Ball Grid Array (MAP-BGA) ...

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TQFP Package Description 3.2 TQFP Package Description Top and bottom views of the TQFP package are shown in Figure 3-1 and Figure 3-2 with their pin-outs. 109 CCD GND D D9 D10 D11 D12 D13 D14 V ...

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A0 BG AA0 AA1 RD WR GND C V CCC BCLK BCLK CLKOUT GND C V CCC EXTAL GND Q XTAL CAS AA2 AA3 NC GND P1 GND P PCAP V CCP RESET HAD0 ...

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TQFP Package Description Pin No. 1 SRD1 or PD4 2 STD1 or PD5 3 SC02 or PC2 4 SC01 or PC1 PINIT/NMI 7 SRD0 or PC4 8 V CCS 9 GND 10 STD0 or PC5 11 SC10 ...

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Table 3-1. DSP56303 TQFP Signal Identification by Pin Number (Continued) Pin Pin Signal Name No. No 100 78 A4 101 79 A5 102 80 V 103 CCA 81 GND 104 105 83 A7 ...

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TQFP Package Description Signal Name 3-6 Table 3-2. DSP56303 TQFP Signal Identification by Name Pin Signal Name No A10 88 CAS A11 89 CLKOUT A12 92 A13 93 A14 94 D10 A15 97 D11 A16 ...

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Table 3-2. DSP56303 TQFP Signal Identification by Name (Continued) Pin Signal Name Signal Name No HREQ/HREQ H3 40 HRRQ/HRRQ HTRQ/HTRQ HA0 33 HA1 32 HA10 30 HA2 31 ...

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TQFP Package Description Signal Name 3-8 Table 3-2. DSP56303 TQFP Signal Identification by Name (Continued) Pin Signal Name No. RAS0 70 SRD1 RAS1 69 STD0 RAS2 51 STD1 RAS3 RESET 44 RXD 13 SC00 12 TIO0 SC01 ...

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TQFP Package Mechanical Drawing 0.20 T L-M 4X Pin 1 144 ident 0.08 T L-M M Section J1-J1 (rotated 90) 144 PL Figure 3-3. DSP56303 Mechanical Information, 144-pin TQFP ...

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MAP-BGA Package Description 3.4 MAP-BGA Package Description Top and bottom views of the MAP-BGA package are shown in Figure 3-4 and Figure 3-5 with their pin-outs SC11 B SRD1 SC12 C SC02 STD1 PINIT SC01 D ...

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D11 D14 D10 D13 D12 CCD GND GND CCD D0 A16 A17 GND GND V A15 A14 GND GND CCA A12 V ...

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MAP-BGA Package Description Pin No. A1 Not Connected (NC), reserved A10 A11 A12 A13 A14 B10 B11 3-12 Table 3-3. DSP56303 MAP-BGA Signal ...

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Table 3-3. DSP56303 MAP-BGA Signal Identification by Pin Number Pin Pin Signal Name No. No. F6 GND H3 F7 GND H4 F8 GND H5 F9 GND H6 F10 GND H7 F11 GND H8 F12 V H9 CCA F13 A14 H10 ...

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MAP-BGA Package Description Table 3-3. DSP56303 MAP-BGA Signal Identification by Pin Number Pin No. L14 M10 M11 M12 Notes: 3-14 Pin Signal Name No HA1, HA8, or PB9 N3 ...

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Table 3-4. DSP56303 MAP-BGA Signal Identification by Name Pin Signal Name Signal Name No. A0 N14 A1 M13 A10 H13 A11 H14 A12 G14 A13 G12 A14 F13 A15 F14 A16 E13 A17 E12 A2 M14 A3 L13 A4 L14 ...

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MAP-BGA Package Description Signal Name 3-16 Table 3-4. DSP56303 MAP-BGA Signal Identification by Name (Continued) Pin Signal Name No. GND F8 GND F9 GND F10 GND F11 GND G4 GND G5 GND G6 GND G7 GND G8 GND G9 GND ...

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Table 3-4. DSP56303 MAP-BGA Signal Identification by Name (Continued) Pin Signal Name Signal Name No. HRW J2 HTRQ/HTRQ K2 HWR/HWR J3 IRQA C4 IRQB A5 IRQC C5 IRQD B5 MODA C4 MODB A5 MODC C5 MODD ...

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MAP-BGA Package Description Signal Name 3-18 Table 3-4. DSP56303 MAP-BGA Signal Identification by Name (Continued) Pin Signal Name No. TDO A4 TIO0 L3 TIO1 L2 TIO2 K3 TMS A3 TRST B4 TXD G3 V F12 CCA V H12 CCA Pin ...

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MAP-BGA Package Mechanical Drawing Figure 3-6. DSP56303 Mechanical Information, 196-pin MAP-BGA Package 3-19 ...

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MAP-BGA Package Mechanical Drawing 3-20 ...

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Chapter 4 Design Considerations 4.1 Thermal Design Considerations Equation 1: Equation 2: An estimate of the chip junction temperature, T this equation Where ambient temperature ° ...

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Electrical Design Considerations A complicating factor is the existence of three common ways to determine the junction-to-case thermal resistance in plastic packages. • To minimize temperature variation across the surface, the thermal resistance is measured from the junction to the ...

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Use the following list of recommendations to ensure correct DSP operation. • Provide a low-impedance path from the board power supply to each board ground to each GND pin. • Use at least six 0.01–0.1 F bypass capacitors positioned as ...

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Power Consumption Considerations 4.3 Power Consumption Considerations Power dissipation is a key issue in portable DSP applications. Some of the factors affecting current consumption are described in this section. Most of the current consumed by CMOS devices is alternating current ...

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PLL Performance Issues The following explanations should be considered as general observations on expected PLL behavior. There is no test that replicates these exact numbers. These observations were measured on a limited number of parts and were not verified ...

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Input (EXTAL) Jitter Requirements 4-6 ...

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Appendix A Power Consumption Benchmark The following benchmark program evaluates DSP56303 power use in a test situation. It enables the PLL, disables the external clock, and uses repeated multiply-accumulate (MAC) instructions with a set of synthetic DSP application data to ...

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Power Consumption Benchmark clr move move move move bset ; sbr dor mac mac add mac mac move _end bra nop nop nop nop PROG_END nop nop XDAT_START ; org ...

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XDAT_END YDAT_START ; org y:0 dc $5B6DA dc $C3F70B dc $6A39E8 dc $81E801 dc $C666A6 dc $46F8E7 dc $AAEC94 dc ...

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Power Consumption Benchmark ; ; EQUATES for DSP56303 I/O registers and ports ; ; Last update: June 11 1995 ; ;************************************************************************** page opt ioequ ;------------------------------------------------------------------------ ; ; ; ;------------------------------------------------------------------------ ; M_HDR EQU $FFFFC9 M_HDDR EQU $FFFFC8 M_PCRC EQU $FFFFBF M_PRRC ...

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EQUATES for Serial Communications Interface (SCI) ; ;------------------------------------------------------------------------ ; Register Addresses M_STXH EQU $FFFF97 ; SCI Transmit Data Register (high) M_STXM EQU $FFFF96 ; SCI Transmit Data Register (middle) M_STXL EQU $FFFF95 ; SCI Transmit Data Register ...

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Power Consumption Benchmark ; M_TX10 EQU $FFFFAC M_TX11 EQU $FFFFAB M_TX12 EQU $FFFFAA M_TSR1 EQU $FFFFA9 M_RX1 EQU $FFFFA8 M_SSISR1 EQU $FFFFA7 M_CRB1 EQU $FFFFA6 M_CRA1 EQU $FFFFA5 M_TSMA1 EQU $FFFFA4 M_TSMB1 EQU $FFFFA3 M_RSMA1 EQU $FFFFA2 M_RSMB1 EQU $FFFFA1 ...

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EQUATES for Exception Processing ; ;------------------------------------------------------------------------ ; Register Addresses M_IPRC EQU $FFFFFF ; Interrupt Priority Register Core M_IPRP EQU $FFFFFE ; Interrupt Priority Register Peripheral ; Interrupt Priority Register Core (IPRC) M_IAL EQU $7 ; IRQA Mode ...

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Power Consumption Benchmark M_TLR0 EQU M_TCPR0 EQU $FFFF8D M_TCR0 EQU ; M_TCSR1 EQU $FFFF8B M_TLR1 EQU M_TCPR1 EQU $FFFF89 M_TCR1 EQU ; M_TCSR2 EQU $FFFF87 M_TLR2 EQU M_TCPR2 EQU $FFFF85 M_TCR2 EQU M_TPLR EQU M_TPCR EQU ; M_TE EQU 0 ...

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M_DDR2 EQU $FFFFE6 ; DMA2 Destination Address Register M_DCO2 EQU $FFFFE5 ; DMA2 Counter M_DCR2 EQU $FFFFE4 ; DMA2 Control Register ; Register Addresses Of DMA4 M_DSR3 EQU $FFFFE3 ; DMA3 Source Address Register M_DDR3 EQU $FFFFE2 ; DMA3 Destination ...

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Power Consumption Benchmark M_FDBA M_FCBA M_FDCH ;------------------------------------------------------------------------ ; ; ; ;------------------------------------------------------------------------ ; M_PCTL EQU $FFFFFD ; M_MF EQU $FFF M_DF EQU $7000 ; Division Factor Bits Mask (DF0-DF2) M_XTLR EQU 15 M_XTLD EQU 16 M_PSTP EQU 17 M_PEN EQU 18 ...

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SR M_CP EQU $c00000; mask for CORE-DMA priority bits in SR M_CA EQU 0 ; Carry M_V EQU 1 ; Overflow M_Z EQU 2 ; Zero M_N EQU 3 ; Negative M_U EQU 4 ...

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Power Consumption Benchmark I_TRAP EQU I_VEC+$08 I_NMI EQU I_VEC+$0A ;------------------------------------------------------------------------ ; Interrupt Request Pins ;------------------------------------------------------------------------ I_IRQA EQU I_VEC+$10 I_IRQB EQU I_VEC+$12 I_IRQC EQU I_VEC+$14 I_IRQD EQU I_VEC+$16 ;------------------------------------------------------------------------ ; DMA Interrupts ;------------------------------------------------------------------------ I_DMA0 EQU I_VEC+$18 I_DMA1 EQU I_VEC+$1A I_DMA2 EQU ...

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Index A ac electrical characteristics 2-4 address bus 1-1 Address Trace mode 2-25 applications iv arbitration bus timings 2-27 B benchmark test algorithm A-1 block diagram i bootstrap ROM iii Boundary Scan (JTAG Port) timing diagram 2-46 bus acquisition timings ...

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Index H Host Interface (HI08) iii , 1-11 Host Port Control Register (HPCR) 1-10 1-12 host port configuration 1-9 usage considerations 1-9 Host Port Control Register (HPCR) 1-10 Host Request Double 1-2 Single 1-2 Host Request (HR) 1-2 I information ...

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JTAG signals 1-18 mode control 1-8 OnCE signals 1-18 PLL signals 1-4 , Reset timing 2-7 2-9 synchronous 2-10 ROM, bootstrap iii S Serial Communication Interface (SCI) iii , 1-2 1-16 Asynchronous mode timing 2-38 Synchronous mode ...

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Ordering Information Consult a Motorola Semiconductor sales office or authorized distributor to determine product availability and place an order. Supply Part Voltage DSP56303 3.3 V I/O Thin Quad Flat Pack (TQFP) Molded Array Process-Ball Grid Array (MAP-BGA) HOW TO REACH ...