C8051F000DK-T Silicon Laboratories Inc, C8051F000DK-T Datasheet - Page 161
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C8051F000DK-T
Manufacturer Part Number
C8051F000DK-T
Description
DEV KIT FOR C8051F000/F001/F002
Manufacturer
Silicon Laboratories Inc
Datasheet
1.C8051F005-TB.pdf
(171 pages)
Specifications of C8051F000DK-T
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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161
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
Bit7:
Bits6-3: UNUSED. Read = 0000b, Write = don’t care.
Bits2-1: CPS1-CPS0: PCA Counter/Timer Pulse Select.
Bit0:
CIDL
R/W
Bit7
CIDL: PCA Counter/Timer Idle Control.
Specifies PCA behavior when CPU is in Idle Mode.
0: PCA continues to function normally while the system controller is in Idle Mode.
1: PCA operation is suspended while the system controller is in Idle Mode.
These bits select the timebase source for the PCA counter.
ECF: PCA Counter/Timer Overflow Interrupt Enable.
This bit sets the masking of the PCA Counter/Timer Overflow (CF) interrupt.
0: Disable the CF interrupt.
1: Enable a PCA Counter/Timer Overflow interrupt request when CF (PCA0CN.7) is set.
CPS1
0
0
1
1
R/W
Bit6
-
CPS0
0
1
0
1
Figure 20.9. PCA0MD: PCA Mode Register
R/W
Bit5
-
Timebase
System clock divided by 12
System clock divided by 4
Timer 0 overflow
High-to-low transitions on ECI (max rate = system clock divided by 4)
R/W
Bit4
-
Rev. 1.7
R/W
Bit3
-
CPS1
R/W
Bit2
CPS0
R/W
Bit1
ECF
R/W
Bit0
SFR Address:
Reset Value
00000000
0xD9
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