C8051F000DK-E Silicon Laboratories Inc, C8051F000DK-E Datasheet - Page 160
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C8051F000DK-E
Manufacturer Part Number
C8051F000DK-E
Description
DEV KIT FOR C8051F000/F001/F002
Manufacturer
Silicon Laboratories Inc
Datasheet
1.C8051F005-TB.pdf
(171 pages)
Specifications of C8051F000DK-E
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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20.3.
The system device may implement one or more Programmable Counter Arrays. Following are detailed descriptions
of the special function registers related to the operation of the PCA. The CIP-51 System Controller section of the
datasheet provides additional information on the SFRs and their use.
Bit7:
Bit6:
Bit5:
Bit4:
Bit3:
Bit2:
Bit1:
Bit0:
R/W
Bit7
CF
Register Descriptions for PCA
CF: PCA Counter/Timer Overflow Flag.
Set by hardware when the PCA Counter/Timer overflows from 0xFFFF to 0x0000. When
the Counter/Timer Overflow (CF) interrupt is enabled, setting this bit causes the CPU to
vector to the CF interrupt service routine. This bit is not automatically cleared by
hardware and must be cleared by software.
CR: PCA Counter/Timer Run Control.
This bit enables/disables the PCA Counter/Timer.
0: PCA Counter/Timer disabled.
1: PCA Counter/Timer enabled.
UNUSED. Read = 0, Write = don’t care.
CCF4: PCA Module 4 Capture/Compare Flag.
This bit is set by hardware when a match or capture occurs. When the CCF interrupt is
enabled, setting this bit causes the CPU to vector to the CCF interrupt service routine. This
bit is not automatically cleared by hardware and must be cleared by software.
CCF3: PCA Module 3 Capture/Compare Flag.
This bit is set by hardware when a match or capture occurs. When the CCF interrupt is
enabled, setting this bit causes the CPU to vector to the CCF interrupt service routine. This
bit is not automatically cleared by hardware and must be cleared by software.
CCF2: PCA Module 2 Capture/Compare Flag.
This bit is set by hardware when a match or capture occurs. When the CCF interrupt is
enabled, setting this bit causes the CPU to vector to the CCF interrupt service routine. This
bit is not automatically cleared by hardware and must be cleared by software.
CCF1: PCA Module 1 Capture/Compare Flag.
This bit is set by hardware when a match or capture occurs. When the CCF interrupt is
enabled, setting this bit causes the CPU to vector to the CCF interrupt service routine. This
bit is not automatically cleared by hardware and must be cleared by software.
CCF0: PCA Module 0 Capture/Compare Flag.
This bit is set by hardware when a match or capture occurs. When the CCF interrupt is
enabled, setting this bit causes the CPU to vector to the CCF interrupt service routine. This
bit is not automatically cleared by hardware and must be cleared by software.
R/W
Bit6
CR
Figure 20.8. PCA0CN: PCA Control Register
R/W
Bit5
-
CCF4
R/W
Bit4
Rev. 1.7
CCF3
R/W
Bit3
CCF2
R/W
Bit2
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
CCF1
R/W
Bit1
(bit addressable)
CCF0
R/W
Bit0
SFR Address:
Reset Value
00000000
0xD8
160
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