AD9515/PCB Analog Devices Inc, AD9515/PCB Datasheet - Page 9

• Manufacturer Part Number: AD9515/PCB
• Description: BOARD EVAL CLOCK 2CHAN 32LFCSP
• Manufacturer: Analog Devices Inc

Specifications of AD9515/PCB

• Design Resources: Low Jitter Sampling Clock Generator for High Performance ADCs Using AD9958/9858 and AD9515 (CN0109)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Parameter
CMOS OUTPUT ADDITIVE TIME JITTER
DELAY BLOCK ADDITIVE TIME JITTER
1
SYNCB, VREF, AND SETUP PINS
Table 6.
Parameter
SYNCB
VREF
S0 TO S10
This value is incremental. That is, it is in addition to the jitter of the LVDS or CMOS output without the delay. To estimate the total jitter, the LVDS or CMOS output jitter
should be added to this value using the root sum of the squares (RSS) method.
CLK = 400 MHz
CLK = 400 MHz
Delay FS = 1.5 ns Fine Adj. 00000
Delay FS = 1.5 ns Fine Adj. 11111
Delay FS = 5 ns Fine Adj. 00000
Delay FS = 5 ns Fine Adj. 11111
Delay FS = 10 ns Fine Adj. 00000
Delay FS = 10 ns Fine Adj. 11111
Logic High
Logic Low
Capacitance
Output Voltage
Levels
CMOS (OUT1) = 100 MHz
Divide = 4
CMOS (OUT1) = 100 MHz
Divide = 4
LVPECL (OUT0) = 50 MHz
0
1/3
2/3
1
Min
2.7
0.62 V
0.2 V
0.55 V
0.9 V
S
S
S
S
1
Typ
2
Min
Max
0.40
0.76 V
0.1 V
0.45 V
0.8 V
S
S
S
S
Typ
290
315
0.71
1.2
1.3
2.7
2.0
2.8
Rev. 0 | Page 9 of 28
Unit
V
V
pF
V
V
V
V
V
Max
Test Conditions/Comments
Minimum − maximum from 0 mA to 1 mA load
Unit
fs rms
fs rms
ps rms
ps rms
ps rms
ps rms
ps rms
ps rms
Test Conditions/Comments
Delay off
Calculated from SNR of ADC method
Calculated from SNR of ADC method
Interferer
100 MHz output; incremental additive jitter
AD9515